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MSP430F2112TRHB Datasheet(PDF) 9 Page - Texas Instruments |
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MSP430F2112TRHB Datasheet(HTML) 9 Page - Texas Instruments |
9 / 22 page MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset vector (0xFFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU enters LPM4 after power--up. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External reset Watchdog Flash key violation PC out of range (see Note 1) PORIFG RSTIFG WDTIFG KEYV (see Note 2) reset 0xFFFE 31, highest NMI Oscillator fault Flash memory access violation NMIIFG OFIFG ACCVIFG (see Notes 2 and 6) (non)maskable (non)maskable (non)maskable 0xFFFC 30 Timer1_A2 TA1CCR0 CCIFG (see Note 3) maskable 0xFFFA 29 Timer1_A2 TA1CCR1 CCIFG, TA1CTL TAIFG (see Notes 2 and 3) maskable 0xFFF8 28 Comparator_A+ CAIFG maskable 0xFFF6 27 Watchdog timer WDTIFG maskable 0xFFF4 26 Timer0_A3 TA0CCR0 CCIFG (see Note 3) maskable 0xFFF2 25 Timer0_A3 TA0CCR1 CCIFG, TA0CCR2 CCIFG, TA0CTL TAIFG (see Notes 2 and 3) maskable 0xFFF0 24 USCI_A0/USCI_B0 receive USCI_B0 I2C status UCA0RXIFG, UCB0RXIFG (see Note 2 and 4) Maskable 0xFFEE 23 USCI_A0/USCI_B0 transmit USCI_B0 I2C receive / transmit UCA0TXIFG, UCB0TXIFG (see Note 2 and 5) Maskable 0xFFEC 22 ADC10 ADC10IFG (see Note 3) maskable 0xFFEA 21 0xFFE8 20 I/O port P2 (eight flags) P2IFG.0toP2IFG.7 (see Notes 2 and 3) maskable 0xFFE6 19 I/O port P1 (eight flags) P1IFG.0toP1IFG.7 (see Notes 2 and 3) maskable 0xFFE4 18 0xFFE2 17 0xFFE0 16 SeeNote7 0xFFDE 15 SeeNote8 0xFFDC to 0xFFC0 14 to 0, lowest NOTES: 1. A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF). 2. Multiple source flags. 3. Interrupt flags are located in the module. 4. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, and UCSTPIFG. 5. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, and UCB0TXIFG. 6. Non--maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot. 7. This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h) disables the erasure of the flash if an invalid password is supplied. 8. The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if necessary. |
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