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TMS470R1VF67AGJZT Datasheet(PDF) 1 Page - Texas Instruments |
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TMS470R1VF67AGJZT Datasheet(HTML) 1 Page - Texas Instruments |
1 / 70 page Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Code Composer Studio is a trademark of Texas Instruments. ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM). All trademarks are the property of their respective owners. † The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device. TMS470R1VF67A 16/32-BIT RISC FLASH MICROCONTROLLER SPNS004I – NOVEMBER 2002 – REVISED OCTOBER 2005 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated High-Performance Static CMOS Technology TMS470R1x 16/32-Bit RISC Core (ARM7TDMI ™) – 24-MHz System Clock (60-MHz Pipeline) – Independent 16/32-Bit Instruction Set – Open Architecture With Third-Party Support – Built-In Debug Module – Utilizes Big-Endian Format Integrated Memory – 512K-Byte Program Flash – Two Banks With 14 Contiguous Sectors – Internal State Machine for Program and Erase – 32K-Byte Static RAM (SRAM) Operating Features – Core Supply Voltage (VCC): 1.81 V - 2.05 V – I/O Supply Voltage (VCCIO): 3.0 V - 3.6 V – Low-Power Modes: STANDBY and HALT – Industrial and Automotive Temperature Ranges 470+ System Module – 32-Bit Address Space Decoding – Bus Supervision for Memory and Peripherals – Analog Watchdog (AWD) Timer – Real-Time Interrupt (RTI) – System Integrity and Failure Detection Direct Memory Access (DMA) Controller – 32 Control Packets and 16 Channels Frequency-Modulated Phase-Locked Loop (FMPLL)-Based Clock Module With Prescaler – Multiply-by-4 or -8 Internal FMPLL Option Seven Communication Interfaces: – Two Serial Peripheral Interfaces (SPIs) – 255 Programmable Baud Rates – Serial Communications Interfaces (SCI) –224 Selectable Baud Rates – Asynchronous/Isosynchronous Modes – Two High-End CAN Controllers: – 32-Mailbox Capacity – Fully Compliant With CAN Protocol, Version 2.0B – Multi-Buffered Serial Peripheral Interface (MibSPI) –128-Word Buffer – Four DMA Channels – Six Chip Selects – Class II Serial Interface (C2SIb) – Two Selectable Data Rates – Normal Mode 10.4 Kbps and 4X Mode 41.6 Kbps High-End Timer (HET) – 32 Programmable I/O Channels: – 30 High-Resolution Pins – 2 Standard-Resolution Pins – High-Resolution Share Feature (XOR) – High-End Timer RAM – 128-Instruction Capacity Two 10-Bit, 16-Channel Multi-Buffered ADCs – 128-Word FIFO Buffer – Single- or Continuous-Conversion Modes –1.55 μs Minimum Sample and Conversion Time – Calibration Mode and Self-Test Features Four External Interrupts Flexible Interrupt Handling 3 Dedicated General-Purpose I/O (GIO) Pins, 1 Input-Only GIO Pin, and 65 Additional Peripheral I/Os Compatible ROM Device (Planned) On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1† (JTAG) Test-Access Port 176-Pin Plastic Ball Grid Array (GJZ Suffix) Development System Support Tools Available – Code Composer Studio ™ Integrated Development Environment (IDE) – HET Assembler and Simulator – Real-Time In-Circuit Emulation – Flash Programming External Clock Prescale (ECP) Module – Programmable Low-Frequency External Clock (CLK) |
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