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T6LD4 Datasheet(PDF) 5 Page - Toshiba Semiconductor |
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T6LD4 Datasheet(HTML) 5 Page - Toshiba Semiconductor |
5 / 11 page T6LD4 2006-09-20 5 Device Operation ● Shift data transfer method Shift data MODE Output Mode U/DPin Input Output Data Transfer Method H DI/O DO/I G1 → G2 → G3 → G4 → ··· → G350 H 350-out L DO/I DI/O G350 → G349 → G348 → ··· → G1 H DI/O DO/I G1 → G2 → G3 → G4 → ··· → G170→ G179 → ··· → G350 L 342-out L DO/I DI/O G350 → G349 → G348 → ···→ G179 → G170 → ··· → G1 The input data (DI/O or DO/I) is latched into the internal register synchronously with the rising edge of the shift clock CPV. At the same time that the data is shifted to the next register at the next rise of CPV, new vertical shift data is latched into. In the output operation, the data in the last shift register (G350 or G1) is output synchronously with the falling edge of CPV. (The output high voltage is the VDD level; the output low voltage is the VSS level.) |
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