March 2006 REVISION 09

SH 10 of 31

Technical Reference Note

AIF - PFC Power Factor

Correction Series

Power Fail Warning Adjust

The level at which a Power Fail Warning occurs can be programmed using the PFW Adjust input (pin 12). If the pin is left

unconnected then the PFW operates at the default factory set value.

The output from the PFW ADJ pin is a 1mA current source. To adjust the PFW threshold, a voltage source (0 – 4Volts) or a

programming resistance (0 – 4Kohm) referenced to s S GND (pin 13) should be connected. This allows adjustment of the

PFW threshold from 280V up to 340V. The value of resistance or voltage required can be read from the graph above.

Clock Signals (CLK IN, CLK OUT)

The PFC’s internal clock is accurate and stable over its full operating range and synchronization is not normally required,

but it can reduce noise in paralleled systems.

Clock signals can be wired in series (the CLK OUT pin of one module to the CLK IN pin of the next etc) in which case all

the modules will be synchronized with the first module in the chain. Alternatively, an external clock signal of TTL level at

1MHz

± 10% can be connected to the CLK IN pins of all the modules.