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DAC5681ZIRGCR Datasheet(PDF) 4 Page - Texas Instruments |
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DAC5681ZIRGCR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 8 page www.ti.com DAC5682Z Data Sheet Reference DAC5681Z SLLS865 – AUGUST 2007 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. D[15..0]N 8, 12, 14, 16, I LVDS negative input data bits 0 through 15. (See D[15:0]P description above) 18, 20, 22, D15N is most significant data bit (MSB) – pin 8 24, 28, 30, D0N is least significant data bit (LSB) – pin 43 32, 34, 36, 38, 41, 43 DCLKP 25 I LVDS positive input clock. Unlike the other LVDS inputs, the DCLKP/N pair is self-biased and does not have an internal termination resistor in order to optimize operation of the DLL circuit. See the “DLL Operation” section. For proper external termination, connect a 100 Ω resistor across LVDS clock source lines followed by series 0.01 μF capacitors connected to each of DCLKP and DCLKN pins (see Figure 2). For best performance, the resistor and capacitors should be placed as close as possible to these pins. DCLKN 26 I LVDS negative input clock. (See the DCLKP description) DVDD 10, 39, 50, I Digital supply voltage. (1.8 V) 63 EXTIO 56 I/O Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD). Used as internal reference output when EXTLO = GND, requires a 0.1 μF decoupling capacitor to AGND when used as reference output. EXTLO 58 O Internal reference ground. Connect to AVDD to disable the internal reference. GND 4, Thermal I Pin 4 and the Thermal Pad located on the bottom of the QFN package is ground for AVDD, DVDD and Pad IOVDD supplies. IOUTA1 52 O A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin. In single DAC mode, outputs appear on the IOUTA1/A2 pair only. IOUTA2 53 O A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1 described above. An input data value of 0x0000 results in a 0mA sink and the most positive voltage on the IOUTA2 pin. IOUTB1 61 O B-Channel DAC current output. See the IOUTA1 description above. IOUTB2 60 O B-Channel DAC complementary current output. See the IOUTA2 description above. IOVDD 9 I Digital I/O supply voltage (3.3V) for pins RESETB, SCLK, SDENB, SDIO, SDO. LPF 64 I PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin may be left open. Set both PLL_bypass and PLL_sleep control bits for reduced power dissipation. RESETB 49 I Resets the chip when low. Internal pull-up. SCLK 47 I Serial interface clock. Internal pull-down. SDENB 48 I Active low serial data enable, always an input to the DAC5681Z. Internal pull-up. SDIO 46 I/O Serial interface data, bi-directional. Default setting sets SDIO as an input. Internal pull-down. SDO 45 O Serial interface data, uni-directional data output, if SDIO is an input. SDO is 3-stated when the 3 pin interface mode is selected (register 0x08 bit 1). Internal pull-down. SYNCP 5 I LVDS SYNC positive input data. The SYNCP/N LVDS pair has an internal 100 Ω termination resistor. By default, the SYNCP/N input must be logic ‘1’ to enable a DAC analog output. See the LVDS SYNCP/N Operation paragraph for a detailed description. SYNCN 6 I LVDS SYNC negative input data. VFUSE 44 I Digital supply voltage. (1.8V) Connect to DVDD pins for normal operation. This supply pin is also used for factory fuse programming. Prior to market release, please refer to the DAC5682Z (dual channel) data sheet SLLS853 for relevant single-channel functional descriptions and performance characteristics on the DAC5681Z device. 4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): DAC5681Z |
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