TC74HC697AP/AF

2007-10-01

3

Truth Table

Inputs

Outputs

CCLR

LOAD

ENP

ENT

CCK

D

U/

RCK

C

R/

G

QA

QB

QC

QD

Function

X

X

X

X

X

X

X

X

H

Z

Z

Z

Z

Z

L

X

X

X

X

X

X

L

L

L

L

L

L

Clear Counter

H

L

X

X

X

X

L

L

a

b

c

d

Load Counter

H

H

H

X

X

X

L

L

H

H

X

H

X

X

L

L

No Change

No Count

H

H

L

L

H

X

L

L

Count Up

Count

H

H

L

L

L

X

L

L

Count Down

Count

H

X

X

X

X

X

L

L

No Change

No Count

X

X

X

X

X

X

H

L

a’

b’

c’

d’

Load Register

X

X

X

X

X

X

H

L

No Change

No Count

X: Don’t care

Z: High impedance

a~d: The level of steady state inputs at inputs A through D respectively.

a’~d’: The level of steady state outputs at internal counter outputs QA’ through QD’ respectively.

RCO

= (

ENT

QD

QC

QB

QA

UP

ENT

QD

QC

QB

QA

UP

⋅

⋅

⋅

⋅

⋅

+

⋅

⋅

⋅

⋅

⋅

)