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STR755FR1H6 Datasheet(PDF) 9 Page - STMicroelectronics |
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STR755FR1H6 Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 84 page STR750Fxx STR751Fxx STR752Fxx STR755Fxx Introduction 9/84 I²C bus The I²C bus interface can operate in multi-master and slave mode. It can support standard and fast modes (up to 400KHz). High speed universal asynch. receiver transmitter (UART) The three UART interfaces are able to communicate at speeds of up to 2 Mbit/s. They provide hardware management of the CTS and RTS signals and have LIN Master capability. To optimize the data transfer between the processor and the peripheral, two FIFOs (receive/transmit) of 16 bytes each have been implemented. One UART can be served by the DMA controller (UART0). Synchronous serial peripheral (SSP) The two SSPs are able to communicate up to 8 Mbit/s (SSP1) or up to 16 Mbit/s (SSP0) in standard full duplex 4-pin interface mode as a master device or up to 2.66 Mbit/s as a slave device. To optimize the data transfer between the processor and the peripheral, two FIFOs (receive/transmit) of 8 x 16 bit words have been implemented. The SSPs support the Motorola SPI or TI SSI protocols. One SSP can be served by the DMA controller (SSP0). Controller area network (CAN) The CAN is compliant with the specification 2.0 part B (active) with a bit rate up to 1Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Up to 32 message objects are handled through an internal RAM buffer. In LQFP64 devices, CAN and USB cannot be connected simultaneously. Universal serial bus (USB) The STR750F embeds a USB device peripheral compatible with the USB Full speed 12Mbs. The USB interface implements a full speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock source is generated from the internal main PLL. VDD must be in the range 3.3V±10% for USB operation. ADC (analog to digital converter) The 10-bit Analog to Digital Converter, converts up to 16 external channels (11 channels in 64-pin devices) in single-shot or scan modes. In scan mode, continuous conversion is performed on a selected group of analog inputs. The minimum conversion time is 3.75 µs (including the sampling time). The ADC can be served by the DMA controller. An analog watchdog feature allows you to very precisely monitor the converted voltage of up to four channels. An IRQ is generated when the converted voltage is outside the programmed thresholds. The events generated by TIM0, TIM2 and PWM timers can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers. |
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