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TMP88CP38ANG Datasheet(PDF) 11 Page - Toshiba Semiconductor |
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TMP88CP38ANG Datasheet(HTML) 11 Page - Toshiba Semiconductor |
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11 / 226 page  TMP88CS38/CM38A/CP38A 2007-09-12 88CS38-11 (2) Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called a “machine cycle”. There are a total of 15 different types of instructions for the TLCS-870/X series: Ranging from 1-cycle instructions which require one machine cycle for execution to 15-cycle instructions which require 15 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. Figure 1.4.6 Machine Cycle 1.4.3 Standby Controller The standby controller starts and stops the switches the main system clock. These modes are controlled by the system control registers (SYSCR1, SYSCR2). Figure 1.4.7 shows the operating mode transition diagram and Figure 1.4.8 shows the system control registers. (1) Single-clock mode In the single-clock mode, the machine cycle time is 4/fc [s] (0.25 μs at fc = 16 MHz). 1. NORMAL mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. 2. IDLE mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain active (Operate using the high-frequency clock). IDLE mode is started by setting IDLE bit in the system control register 2 (SYSCR2), and IDLE1 mode is released to NORMAL mode by an interrupt request from on-chip peripherals or external interrupt inputs. When IMF (Interrupt master enable flag) is “1” (Interrupt enable), the execution will resume upon acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When IMF is “0” (Interrupt disable), the execution will resume with the instruction which follows IDLE mode start instruction. 3. STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with the lowest power consumption during this mode. STOP mode is started by setting STOP bit in the system control register 1 (SYSCR1), and STOP mode is released by an input (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warm-up period is completed, the execution resumes with the next instruction which follows the STOP mode start instruction. 1/fc Main system clock fm State Machine cycle (0.25 μs at fc = 16 MHz) S3 S2 S1 S0 S3 S2 S1 S0 |
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