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DP80390 Datasheet(PDF) 2 Page - Digital Core Design |
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DP80390 Datasheet(HTML) 2 Page - Digital Core Design |
2 / 10 page All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. ● ● ● ● ● ○ ○ ○ ○ ○ ○ ○ ○ ○ ● ○ ○ ○ ● ○ ○ ○ ● ○ ○ ● ○ ○ ○ ● ○ ○ ○ ○ http://www.DigitalCoreDesign.com http://www.dcd.pl PERIPHERALS Interface for additional Special Function Registers Fully synthesizable, static synchronous design with positive edge clocking and no internal tri-states Scan test ready 2.0 GHz virtual clock frequency in a 0.25u technological process DoCD™ debug unit Processor execution control Run Halt Step into instruction Skip instruction Read-write all processor contents Program Counter (PC) Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Code execution breakpoints one real-time PC breakpoint unlimited number of real-time OPCODE break- points Hardware execution watch-point one at Internal (direct) Data Memory one at Special Function Registers (SFRs) one at External Data Memory Hardware watch-points activated at a certain address by any write into memory address by any read from memory address by write into memory a required data address by read from memory a required data Unlimited number of software watch-points Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Unlimited number of software breakpoints Program Memory(PC) Automatic adjustment of debug data transfer speed rate between HAD and Silicon JTAG Communication interface Power Management Unit Power management mode Switchback feature Stop mode Interrupt Controller 2 priority levels 2 external interrupt sources 3 interrupt sources from peripherals Four 8-bit I/O Ports Bit addressable data direction for each line Read/write of single line and 8-bit group Two 16-bit timer/counters Timers clocked by internal source Auto reload 8-bit timers Externally gated event counters Full-duplex serial port Synchronous mode, fixed baud rate 8-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, variable baud rate CONFIGURATION The following parameters of the DP80390 core can be easy adjusted to requirements of dedi- cated application and technology. Configura- tion of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. - synchronous • Internal Program Memory type - asynchronous - • Internal Program ROM Memory size - 0 - 64kB - • Internal Program RAM Memory size - 0 - 64kB - true • Internal Program Memory fixed size - false • Interrupts - subroutines location - used • Power Management Mode - unused - used • Stop mode - unused - used • DoCD™ debug unit - unused Besides mentioned above parameters all available peripherals and external interrupts can be excluded from the core by changing appropriate constants in package file. |
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