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D16550 Datasheet(PDF) 1 Page - Digital Core Design |
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D16550 Datasheet(HTML) 1 Page - Digital Core Design |
1 / 7 page All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl D D1 16 65 55 50 0 Configurable UART with FIFO ver 2.08 OVERVIEW The D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16550 performs serial-to- parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). D16550 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The D16550 has complete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link. The separate BAUD CLK line allow to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency. Two DMA modes are supported: single transfer and multi-transfer. These modes allow UART to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers. The configuration capability allows user to enable or disable during Synthesis process the Modem Control Logic and FIFO's Control Logic, change the FIFO size. So in applications with area limitation and where the UART works only in 16450 mode, disabling Modem Control and FIFO's allow to save about 50% of logic resources. The D16550 has universal microcontroller interface, allows correct communication with D16550 no matter how D16550 clock is related to microcontroller clock. The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface D16550 core implementation and verification are very simply, by eliminating a number of clock trees in complete system. |
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