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BUF01900AIDRCR Datasheet(PDF) 11 Page - Texas Instruments |
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BUF01900AIDRCR Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 25 page  BUF01900 BUF01901 SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 www.ti.com 11 ACQUIRE OF OTP MEMORY An acquire command updates the DAC output to the value stored in OTP memory. If the OTP memory has not been programmed, the DAC output code is ‘0000000000’. Figure 19 shows the timing diagram for the acquire command. Acquire Command 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The device will acknowledge this byte. 3. Send the acquire command. Bits D7—D5 must be set to 001. Bits D4—D0 do not have meaning. This byte will be acknowledged. 4. Send a STOP condition on the bus. Writing OTP Memory The BUF0190x is able to write to the OTP memory a maxi- mum of four times. Writing to the OTP memory a fourth time uses all available memory and disables the ability to perform additional writes (see table 3). A reset or acquire command updates the DAC output to the most recently written OTP memory value. When programming the OTP memory, the analog supply voltage must be between 8.5V and 18V. Write commands are performed by setting the read/write bit LOW. To write to OTP memory: 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF0190x acknowledges this byte. 3. Send two bytes of data for the OTP memory. Begin by sending the most significant byte first (bits D15 —D8, of which only bits D9 and D8 are data bits, and bits D15 —D13 must be 010), followed by the least significant byte (bits D7 —D0). The register updates after receiving the second byte. 4. Send a STOP condition on the bus. The BUF0190x acknowledges each data byte. If the mas- ter terminates communication early by sending a STOP or START condition on the bus, the specified OTP register will not be updated. Writing an OTP register updates the DAC output voltage. Programming timing is taken from the two-wire bus. Therefore, the master must provide correct timing on the bus to ensure data is successfully written into OTP memory. Figure 20 shows the timing requirements for tim- ing when the OTP write supply and OTP write signal are active. |
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