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ZL38005QCG1 Datasheet(PDF) 2 Page - Zarlink Semiconductor Inc |
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ZL38005QCG1 Datasheet(HTML) 2 Page - Zarlink Semiconductor Inc |
2 / 8 page ZL38005 Data Sheet 2 Zarlink Semiconductor Inc. 1.0 Functional Description The ZL38005 is a hardware platform designed to support advanced acoustic echo canceller (with noise reduction) firmware applications available from Zarlink Semiconductor. These applications are resident in external memory and are down-loaded by the ZL38005 resident boot code during initialization. The firmware product and manual available at the release of this data sheet is the ZLS38501: Acoustic Echo Canceller with Noise Reduction. If these applications do not meet your requirements, please contact your local Zarlink Sales Office for the latest firmware releases. The ZL38005 Advanced Acoustic Echo Canceller with Noise Reduction platform integrates Zarlink’s Voice Processor (ZVP) DSP Core with a number of internal peripherals. These peripherals include the following: • Two independent ∆Σ CODECs • Two PCM ports - ST BUS, GCI, McBSP or SSI operation •An I2S interface port • A 2048 tap Filter Co-processor (LMS, FIR and FAP realizations) • Two Auxiliary Timers and a Watchdog Timer • 11 GPIO pins • A UART interface • A Slave SPI port and a Master SPI port • A timing block that supports master and slave operation • An IEEE - 1149.1 compatible JTAG port The DSP Core can process up to four 8-bit audio channels, two 16-bit audio channels or two 8-bit and one 16-bit audio channel. These audio channels may originate and terminate with the Σ∆ CODECs, or be communicated to and from the DSP Core through the PCM ports or the I2S port. |
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