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© ZMD AG, 2006

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31010

Datasheet

1.4.2

Output Buffer

A rail-to-rail op amp configured as a unity gain buffer can drive resistive loads (whether pull-up or pull-down)

as low as 2.5k

Ω and capacitances up to 15nF. In addition, to limit the error due to amplifier offset voltage, an

error compensation circuit is included which tracks and reduces offset voltage to < 1mV.

1.4.3

Voltage Reference Block

This block uses the absolute reference voltage provided by the bandgap to produce two regulated on-chip

voltage references. A 1V reference is used for the output DAC high reference when the part is configured in

0-1V analog output mode. For this reason, the 1V reference must be very accurate and includes trim so that

its value can be trimmed within +/- 2mV of 1.00V. The 1V reference is also used as the on-chip reference for

the JFET regulator block so the regulation set point of the JFET regulator can be fine tuned using the 1V trim.

1V Reference Trim (1V vs. Trim for Nominal Process Run):

1Vref_trim3

1Vref_trim2

1Vreft_trim1

1Vref_trim0

1Vref deltaV

5Vref deltaV

1

1

1

1

-0.0184

-0.0920

1

1

1

0

-0.0161

-0.0805

1

1

0

1

-0.0138

-0.0690

1

1

0

0

-0.0115

-0.0575

1

0

1

1

-0.0092

-0.0460

1

0

1

0

-0.0069

-0.0345

1

0

0

1

-0.0046

-0.0230

1

0

0

0

-0.0023

-0.0115

0

1

1

1

Nominal

Nominal

0

1

1

0

+0.0023

+0.0115

0

1

0

1

+0.0046

+0.0230

0

1

0

0

+0.0069

+0.0345

0

0

1

1

+0.0092

+0.0460

0

0

1

0

+0.0115

+0.0575

0

0

0

1

+0.0138

+0.0690

0

0

0

0

+0.0161

+0.0805

Sample: Programming “0000”

→ the trimmed voltage = nominal value + 0.0161V

1.5

Clock Generator / Power On Reset (CLKPOR)

If the power supply exceeds 2.5V (maximum), the reset signal de-asserts and the clock generator starts

working at a frequency of approximately 512kHz (±20%). The exact value only influences the conversion

cycle time and communication to the outside world but not the accuracy of signal processing. In addition, to

block.