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ISL9216 Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL9216 Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 33 page 9 FN6488.1 November 2, 2007 WAKE-UP/SLEEP SPECIFICATIONS Device WKUP Pin Voltage Threshold (WKUP pin active HIGH rising edge) VWKUP1 WKUP pin rising edge (WKPOL = 1) Device wakes up and sets WKUP flag HIGH. (ISL9216 only) 3.5 5.0 6.5 V Device WKUP Pin Hysteresis (WKUP pin active HIGH) VWKUP1H WKUP pin falling edge hysteresis (WKPOL = 1) sets WKUP flag LOW (does not automatically enter sleep mode) (ISL9216 only) 100 mV Internal Resistor on WKUP RWKUP Resistance from WKUP pin to VSS (WKPOL = 1) (ISL9216 only) 130 230 330 k Ω Device WKUP Pin Voltage Threshold (WKUP pin active LOW - Falling Edge) VWKUP2 WKUP pin falling edge (WKPOL = 0) Device wakes up and sets WKUP flag HIGH. VCELL1 - 2.6 VCELL1 - 2.0 VCELL1 - 1.2 V Device WKUP Pin Hysteresis (WKUP pin active LOW) VWKUP2H WKUP pin rising edge hysteresis (WKPOL = 0) sets WKUP flag LOW (does not automatically enter sleep mode) 200 mV Device Wake-up Delay tWKUP Delay after voltage on WKUP pin crosses the threshold (rising or falling) before activating the WKUP bit. 20 40 60 ms FET CONTROL SPECIFICATIONS (For VCELL1, VCELL2, VCELL3 voltages from 2.8V to 4.3V - ISL9216 only) Control Outputs Response Time (CFET, DFET) tCO Bit 0 to start of control signal (DFET) Bit 1 to start of control signal (CFET) 1.0 µs CFET Gate Voltage VCFET No load on CFET VCELL3 - 0.5 VCELL3 V DFET Gate Voltage VDFET No load on DFET VCELL3 - 0.5 VCELL3 V FET Turn-on Current (DFET) IDF(ON) DFET voltage = 0 to VCELL3 - 1.5V 80 130 400 µA FET Turn-on Current (CFET) ICF(ON) CFET voltage = 0 to VCELL3 - 1.5V 80 200 400 µA FET Turn-off Current (DFET) IDF(OFF) DFET voltage = VDFET to 1V 100 180 mA DFET Resistance to VSS RDF(OFF) VDFET <1V (When turning off the FET) 11 Ω SERIAL INTERFACE CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) SCL Clock Frequency fSCL 100 kHz SCL Falling Edge to SDA Output Data Valid tAA From SCL falling crossing VIH(min), until SDA exits the VIL(max) to VIH(min) window. 3.5 µs Time the Bus Must be Free Before Start of New Transmission tBUF SDA crossing VIH(min) during a STOP condition to SDA crossing VIH(min) during the following START condition. 4.7 µs Clock LOW Time tLOW Measured at the VIL(max) crossing. 4.7 µs Clock HIGH Time tHIGH Measured at the VIH(min) crossing. 4.0 µs Start Condition Setup Time tSU:STA SCL rising edge to SDA falling edge. Both crossing the VIH(min) level. 4.7 µs Start Condition Hold Time tHD:STA From SDA falling edge crossing VIL(max) to SCL falling edge crossing VIH(min). 4.0 µs Input Data Setup Time tSU:DAT From SDA exiting the VIL(max) to VIH(min) window to SCL rising edge crossing VIL(min). 250 ns Input Data Hold Time tHD:DAT From SCL rising edge crossing VIH(min) to SDA entering the VIL(max) to VIH(min) window. 300 ns Stop Condition Setup Time tSU:STO From SCL rising edge crossing VIH(min) to SDA rising edge crossing VIL(max). 4.0 µs Operating Specifications All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating Conditions, Unless Otherwise Specified. (Continued) DESCRIPTION SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ISL9216, ISL9217 |
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Similar Description - ISL9216 |
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