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TMS470R1VF448PZQ Datasheet(PDF) 9 Page - Texas Instruments |
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TMS470R1VF448PZQ Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 60 page  TMS470R1VF448 16/32-BIT RISC FLASH MICROCONTROLLER SPNS111A – OCTOBER 2005 – REVISED AUGUST 2006 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 Terminal Functions (Continued) † PWR = power, GND = ground, REF = reference voltage, NC = no connect ‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high. § IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.) TERMINAL INPUT VOLTAGE†‡ OUTPUT CURRENT†‡ INTERNAL PULLUP/ PULLDOWN§ DESCRIPTION NAME PIN NO. MULTI-BUFFERED SERIAL PERIPHERAL INTERFACE (MIBSPI) (CONTINUED) MIBSPISCS[0] 2 3.3-V 2mA MibSPI slave chip select. Can be programmed as a GIO pin. If pins MIBSPISCS[4:0] are not externally pulled up or down, they need to be driven as output LOW for reduced power consumption in low power mode. MIBSPISCS[1] 91 MIBSPISCS[2] 97 MIBSPISCS[3] 98 MIBSPISCS[4] 99 MIBSPISCS[5] 100 MibSPI slave chip select. If pins MIBSPISCS[7:5] are not externally pulled up or down, they need to be driven as output LOW for reduced power consumption in low power mode. MIBSPISCS[6] 19 MIBSPISCS[7] 20 ZERO-PIN PHASE-LOCKED LOOP (ZPLL) OSCIN 8 1.8-V Crystal connection pin or external clock input OSCOUT 7 1.8-V O External crystal connection pin PLLDIS 51 3.3-V IPD (100 μA) Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator becomes the system clock. If not in bypass mode, TI recommends that this pin be connected to ground or pulled down to ground by an external resistor. SERIAL COMMUNICATIONS INTERFACE 1 (SCI1) SCI1CLK 61 3.3-V 2mA IPD (20 μA) SCI1 clock. SCI1CLK can be programmed as a GIO pin. SCI1RX 63 IPU (20 μA) SCI1 data receive. SCI1RX can be programmed as a GIO pin. SCI1TX 62 SCI1 data transmit. SCI1TX can be programmed as a GIO pin. SERIAL COMMUNICATIONS INTERFACE 2 (SCI2) SCI2RX 32 3.3-V 2mA IPU (20 μA) SCI2 data receive. SCI2RX can be programmed as a GIO pin. SCI2TX 33 SCI2 data transmit. SCI2TX can be programmed as a GIO pin. SYSTEM MODULE (SYS) CLKOUT 58 3.3-V 8mA IPD (20 μA) Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of SYSCLK, ICLK, or MCLK. PORRST 21 3.3-V IPD (20 μA) Input master chip power-up reset. External VCC monitor circuitry must assert a power-on reset. RST 10 3.3-V 4mA IPU (100 μA) Bidirectional reset. The internal circuitry can assert a reset, and an external system reset can assert a device reset. On this pin, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor be connected to this pin. WATCHDOG/REAL-TIME INTERRUPT (WD/RTI) AWD 3.3-V 8mA IPD (20 μA) Analog watchdog reset. The AWD pin provides a system reset if the WD KEY is not written in time by the system, providing an external RC network circuit is connected. If the user is not using AWD, For more details on the external RC network circuit, see the TMS470R1x System Module Reference Guide (literature number SPNU189). The AWD signal is only connected to the pad and not to a package pin. |
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