CXK79M72C165GB / CXK79M36C165GB

Preliminary

18Mb 1x1Dp, LVCMOS, rev 1.3

6 / 29

November 18, 2003

Clock Truth Table

Notes:

1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

2. “***” indicates that the DQ input requirement or output state and the CQ output state are determined by the previous operation.

3. “---” indicates that the DQ input requirement or output state and the CQ output state are determined by the next operation.

4. If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”.

5. If one or more Bx = 0 then B = “T” else B = “F”.

6. DQs are tri-stated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.

7. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled.

8. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four

(4) distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal ad-

dress wraps back to the initial external (base) address.

CK

E1

E

ADV

W

B

Previous

Operation

Current Operation

DQ/CQ

DQ/CQ

DQ/CQ

↑

X

F

0

X

X

X

Bank Deselect

***

Hi-Z

---

↑

X

X

1

X

X

Bank Deselect

Bank Deselect (Continue)

Hi-Z

Hi-Z

---

↑

1

T

0

X

X

X

Deselect

***

Hi-Z/CQ

---

↑

X

X

1

X

X

Deselect

Deselect (Continue)

Hi-Z/CQ

Hi-Z/CQ

---

↑

0T

0

0

T

X

Write

Loads new address

Stores DQx if Bx = 0

***

Hi-Z/CQ

D1/---

↑

0T

0

0

F

X

Write (Abort)

Loads new address

No data stored

***

Hi-Z/CQ

X/---

↑

X

X

1

X

T

Write

Write Continue

Increments address by 1

Stores DQx if Bx = 0

Hi-Z/CQ

D1/CQ

D2/---

↑

X

X

1

X

F

Write

Write Continue (Abort)

Increments address by 1

No data stored

Hi-Z/CQ

D1/CQ

X/---

↑

0T

0

1

X

X

Read

Loads new address

***

Q1/CQ

---

↑

X

X

1

X

X

Read

Read Continue

Increments address by 1

Q1/CQ

Q2/CQ

---