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ES6425 Datasheet(PDF) 4 Page - ESS Technology,Inc |
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ES6425 Datasheet(HTML) 4 Page - ESS Technology,Inc |
4 / 8 page 4 SAM0529-091305 ESS Technology, Inc. ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION TSD1 36 O Audio transmit serial data output 1. SEL_PLL1 I Pull up to VCC via 4.7-k Ω resistor for proper operation; read during reset. TSD2 37 O Audio transmit serial data output 2. This pin must be pulled down to VSS via a 4.7-k Ω resistor for proper operation. MCLK 39 I/O Audio master clock for audio DAC. TBCK 40 I/O Audio transmit bit clock. TBCK is an input during reset and subsequently is programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4). SPDIF 41 O S/PDIF output. SEL_PLL3 I Pull down to ground via 4.7-k Ω resistor for proper operation; read during reset. NC 38, 42 — No connect. RSD 45 I Audio receive serial data; (5V tolerant input). RWS 46 I Audio receive frame sync; (5V tolerant input). RBCK 47 I Audio receive bit clock; (5V tolerant input). CAMIN3 48 I Camera and YUV input 3. XIN 49 I 27-MHz crystal input. XOUT 50 O 27-MHz crystal output. AVEE 51 P Analog power for PLL. AVSS 52 G Analog ground for PLL. DMA[11:0] 53-58, 61-66 O DRAM address bus. DCAS# 69 O DRAM column address strobe (active-low). DOE# 70 O DRAM output enable (active-low). DSCK_EN O DRAM clock enable. DWE# 71 O DRAM write enable (active-low). DRAS# 72 O DRAM row address strobe (active-low). DMBS0 73 O SDRAM bank select 0. DMBS1 74 O SDRAM bank select 1. DB[15:0] 77-82, 85-90, 93-96 I/O DRAM data bus. DCS[1:0]# 97,100 O SDRAM chip select (active-low). DQM 101 O Data input/output mask. DSCK 102 O Output clock to SDRAM. DCLK 105 I Clock input to PLL; (5V tolerant input). Table 1 ES6425 Pin Description (Continued) Name Pin Numbers I/O Definition |
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