Rev. 1.4 November 2007

RDIMM

DDR2 SDRAM

4 of 26

1.0 DDR2 Registered DIMM Ordering Information

Note :

1. “Z” of Part number(11th digit) stand for Lead-free products. and "J" of Part number(11th digit) stand for dual-die package products.

2. “3” of Part number(12th digit) stand for Non-parity Register products. and "A" of Part number(12th digit) stand for Parity Register products.

3. "92" of Part number(3~4th digit) stand for VLP(Very Low Profile) Register products.

Part Number

Density

Organization

Component Composition

Number of Rank

Parity Register

Height

M393T5663CZ3-CD5/CC

2GB

256Mx72

128Mx8(K4T1G084QC)*18EA

2

X

30.00mm

M393T5663CZA-CF7/E6

2GB

256Mx72

128Mx8(K4T1G084QC)*18EA

2

O

30.00mm

M393T5660CZ3-CD5/CC

2GB

256Mx72

256Mx4(K4T1G044QC)*18EA

1

X

30.00mm

M393T5660CZA-CF7/E6

2GB

256Mx72

256Mx4(K4T1G044QC)*18EA

1

O

30.00mm

M393T5160CZ3-CD5/CC

4GB

512Mx72

256Mx4(K4T1G044QC)*36EA

2

X

30.00mm

M393T5160CZA-CF7/E6

4GB

512Mx72

256Mx4(K4T1G044QC)*36EA

2

O

30.00mm

M392T5160CJA-CF7/E6

4GB

512Mx72

DDP512Mx4(K4T2G044QC)*18EA

2

O

18.30mm

M393T1G60CJA-CE6/D5

8GB

1Gx72

DDP512Mx4(K4T1G044QC)*36EA

4

O

30.00mm

Organization

Row Address

Column Address

Bank Address

Auto Precharge

256Mx4(1Gb) based Module

A0-A13

A0-A9, A11

BA0-BA2

A10

128Mx8(1Gb) based Module

A0-A13

A0-A9

BA0-BA2

A10

• Performance range

• JEDEC standard 1.8V ± 0.1V Power Supply

•8 Banks

• Posted CAS

• Programmable CAS Latency: 3, 4, 5, 6

• Programmable Additive Latency: 0, 1 , 2 , 3, 4 and 5

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination with selectable values(50/75/150 ohms or disable)

• PASR(Partial Array Self Refresh)

- support High Temperature Self-Refresh rate enable feature

• Serial presence detect with EEPROM

• DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8

• All of Lead-free products are compliant for RoHS

Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.

F7(DDR2-800)

E6(DDR2-667)

D5(DDR2-533)

CC(DDR2-400)

Unit

Speed@CL3

-

400

400

400

Mbps

Speed@CL4

533

533

533

400

Mbps

Speed@CL5

667

667

-

-

Mbps

Speed@CL6

800

-

-

-

Mbps

CL-tRCD-tRP

6-6-6

5-5-5

4-4-4

3-3-3

CK

2.0 Features

3.0 Address Configuration