Electronic Components Datasheet Search |
|
74AUP1G00 Datasheet(PDF) 11 Page - NXP Semiconductors |
|
74AUP1G00 Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 16 page 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 11 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate 13. Package outline Fig 9. Package outline SOT353-1 (TSSOP5) UNIT A1 A max. A2 A3 bp L HE Lp wy v ce D(1) E(1) Z(1) θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.1 0 1.0 0.8 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 e1 1.3 2.25 2.0 0.60 0.15 7 ° 0 ° 0.1 0.1 0.3 0.425 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 0.46 0.21 SOT353-1 MO-203 SC-88A 00-09-01 03-02-19 w M bp D Z e e1 0.15 13 5 4 θ A A2 A1 Lp (A3) detail X L HE E c v M A X A y 1.5 3 mm 0 scale TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 1.1 |
Similar Part No. - 74AUP1G00 |
|
Similar Description - 74AUP1G00 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |