Buffered, Fast-Settling, Quad,

12-/10-/8-Bit, Voltage-Output DACs

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5

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

POWER REQUIREMENTS

Analog Supply Voltage

Range

2.70

5.25

V

Digital Supply Voltage

Range

1.8

V

Unity gain

0.9

1.6

SLOW mode, all digital inputs

Force sense

1.6

2.4

Unity gain

1.6

4

Operating Supply

Current

+

FAST mode, all digital inputs

Force sense

2.3

4

mA

Shutdown Supply

Current

+

DACs in shutdown mode

0.5

1

µA

Note 1: For the force-sense versions, FB_ is connected to its respective OUT_, and VOUT (max) = VREF / 2, unless otherwise noted.

Note 2: Linearity guaranteed from decimal code 250 to code 4095 for the MAX5580A/MAX5581A (12 bit, A grade), code 40 to code

4095 for the MAX5580B/MAX5581B (12 bit, B grade), code 20 to code 1023 for the MAX5582/MAX5583 (10 bit), and code 5

to code 255 for the MAX5584/MAX5585 (8 bit).

Note 3: Represents the functional range. The linearity is guaranteed at VREF = 2.5V (for AVDD from 2.7V to 5.25V), and VREF =

4.096V (for AVDD = 4.5V to 5.25V). See the Typical Operating Characteristics section for linearity at other voltages.

Note 4: Guaranteed by design.

Note 5: The reference -3dB bandwidth is measured with a 0.1VP-P sine wave on VREF and with full-scale input code.

Note 6: DC crosstalk is measured as follows: outputs of DACA–DACD are set to full scale and the output of DACD is measured.

While keeping DACD unchanged, the outputs of DACA–DACC are transitioned to zero scale and the

∆VOUT of DACD

is measured.