High-Bandwidth, Quad DPDT Switches

8

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Timing Circuits/Timing Diagrams

tr < 5ns

tf < 5ns

50%

0V

LOGIC

INPUT

COM_

GND

IN_

(

)

V+

0V

NO_

OR NC_

SWITCH

OUTPUT

LOGIC

INPUT

IN DEPENDS ON SWITCH CONFIGURATION;

INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

V+

V+

MAX4760

MAX4761

50%

Figure 2. Switching Time

50%

V+

0V

LOGIC

INPUT

LOGIC

INPUT

GND

NO_

IN_

NC_

V+

V+

COM_

MAX4760

MAX4761

Figure 3. Break-Before-Make Interval