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74LVC2G14GW Datasheet(PDF) 10 Page - NXP Semiconductors |
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74LVC2G14GW Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 17 page 74LVC2G14_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 4 September 2007 10 of 17 NXP Semiconductors 74LVC2G14 Dual inverting Schmitt trigger with 5 V tolerant input 15. Application information The slow input rise and fall times cause additional power dissipation, which can be calculated using the following formula: Padd =fi × (tr ×∆ICC(AV) +tf ×∆ICC(AV)) × VCC where: Padd = additional power dissipation (µW); fi = input frequency (MHz); tr = input rise time (ns); 10 % to 90 %; tf = input fall time (ns); 90 % to 10 %; ∆I CC(AV) = average additional supply current (µA). ∆I CC(AV) differs with positive or negative input transitions, as shown in Figure 12. An example of a relaxation circuit using the 74LVC2G14 is shown in Figure 13. Linear change of VI between 0.8 V to 2.0 V. All values given are typical unless otherwise specified. (1) Positive-going edge. (2) Negative-going edge. Fig 12. Average ICC as a function of VCC 23 4 6 50 0 40 5 30 20 10 mnb086 ∆ICC(AV) (mA) VCC (V) (1) (2) Fig 13. Relaxation oscillator mna035 R C f 1 T --- 1 0.8 RC × ---------------------- ≈ = |
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