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74LVC1G53 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVC1G53 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 22 page 74LVC1G53_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 29 August 2007 3 of 22 NXP Semiconductors 74LVC1G53 2-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 4. Pin configuration SOT833-1 (XSON8) 74LVC1G53 ZVCC EY0 GND Y1 GND S 001aad388 1 2 3 4 6 5 8 7 74LVC1G53 Y1 Y0 VCC S GND E Z GND 001aad389 36 27 18 45 Transparent top view Fig 5. Pin configuration SOT902-1 (XQFN8) 001aag459 E Y1 Z GND Y0 S Transparent top view 3 6 1 5 7 2 terminal 1 index area 74LVC1G53 Table 3. Pin description Symbol Pin Description SOT505-2, SOT765-1 and SOT833-1 SOT902-1 Z 1 7 common output or input E 2 6 enable input (active LOW) GND 3 5 ground (0 V) GND 4 4 ground (0 V) S 5 3 select input |
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