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DS26524G Datasheet(PDF) 9 Page - Maxim Integrated Products |
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DS26524G Datasheet(HTML) 9 Page - Maxim Integrated Products |
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9 / 273 page  DS26524 Quad T1/E1/J1 Transceiver 9 of 273 1. DETAILED DESCRIPTION The DS26524 is a 4-port monolithic device featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each transceiver is composed of a line interface unit, framer, HDLC controller, elastic store, and a TDM backplane interface. The DS26524 is controlled via an 8-bit parallel port. Internal impedance matching is provided for both transmit and receive paths, reducing external component count. The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well as CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75 Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock and data from the network. The receive sensitivity adjusts automatically to the incoming signal level and can be programmed for 0dB to -43dB or 0dB to -12dB for E1 applications and 0dB to -15dB or 0dB to -36dB for T1 applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a T1 or E1 clock rate, or multiple thereof, for both E1 and T1 applications, and can be placed in either transmit or receive data paths. On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receive- side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock, data, and frame-sync signals to the backplane interface section. Both transmit and receive paths have access to an HDLC controller. The HDLC controller transmits and receives data via the framer block. The HDLC controller can be assigned to any time slot, a portion of a time slot, or to FDL (T1) or Sa bits (E1). Each controller has 64-byte FIFOs, reducing the amount of processor overhead required to manage the flow of data. The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions (asynchronous interface). The interleave bus option (IBO) is provided to allow up to eight transceivers to share a high-speed backplane. The DS26524 also contains an internal clock adapter useful for the creation of a synchronous, high-frequency backplane timing source. The parallel port provides access for configuration and status of all the DS26524’s features. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection. 1.1 Major Operating Modes The DS26524 has two major modes of operation: T1 mode and E1 mode. The mode of operation for the LIU is configured in the LIU Transmit Receive Control register (LTRCR). The mode of operation for the framer is configured in the Transmit Master Mode register (TMMR). J1 operation is a special case of T1 operating mode. |
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Similar Description - DS26524G |
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