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PI7C8150BNDI-33 Datasheet(PDF) 3 Page - Pericom Semiconductor Corporation |
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PI7C8150BNDI-33 Datasheet(HTML) 3 Page - Pericom Semiconductor Corporation |
3 / 108 page PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Page 3 of 108 APRIL 2006 – Revision 2.02 REVISION HISTORY Date Revision Number Description 03/26/03 1.00 First Release of Data Sheet 05/14/03 1.01 Correction to description for bit[0] at offset 48h. Changed from Memory Read Flow Through Disable to Memory Read Flow Through Enable. Added reset condition to offset 4Ch, bits [31:28] 06/10/03 1.02 Revised descriptions and added ordering information for PI7C8150B-33 (33MHz) device Revised temperature support to industrial temperature 06/25/03 1.03 Revised temperature support back to extended commercial range (0C to 85C) Corrected pin descriptions for S_M66EN, P_M66EN, and S_CLKOUT. 07/31/03 1.031 Corrected MS0 and MS1 pin assignments on Table 2.4. MS0 should be B14 and MS1 should be R16. Added PBGA pin assignments to signal descriptions in Section 2.2. Revised power consumption specifications in section 17.6 Revised TDELAY specifications in sections 17.4 and 17.5 10/20/03 1.04 Modified spacing on a few chapters. No changes to content. 02/13/04 1.05 Corrected VDD and VSS pin assignments on Table 2.2.7. Removed pins 106 and 155 (R16 and B14) as these should be MS1 and MS0 respectively. 05/20/04 1.06 Added Industrial temp and Pb-free parts in the Ordering Information Added Ambient Temperature spec for PI7C8150BI 07/06/04 1.061 Added industrial temp and Pb-free descriptions to the features section in the introduction 08/12/04 1.07 Revised register description bits[31:24] offset 18h - Secondary Latency Timer Register (section 14.1.13) Revised register description for bits[3:2] offset 48h – Extended Chip Control Register (section 14.1.31) 09/23/04 2.00 Corrected configuration register offset 80h (bit[15:0] is secondary bus master timeout counter and bit[31:16] is primary bus master timeout counter) Revised and added further descriptions for bit[15:0] offset 80h and bit[31:16] offset 80h 01/10/05 2.01 Corrected Note 4 to show REQ_L has a setup time of 12ns and GNT_L has a setup time of 10ns (section 17.3) 04/05/06 2.02 Removed ‘Advance Information’ title from headers Removed email (solutions@pericom.com) link Revised PCI Local Bus specification compliance to 2.3 06-0044 |
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