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PI7C8150BMA Datasheet(PDF) 8 Page - Pericom Semiconductor Corporation |
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PI7C8150BMA Datasheet(HTML) 8 Page - Pericom Semiconductor Corporation |
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8 / 108 page  PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Page 8 of 108 APRIL 2006 – Revision 2.02 14.1.44 SECONDARY BUS MASTER TIMEOUT COUNTER – OFFSET 80h....................... 91 14.1.45 PRIMARY BUS MASTER TIMEOUT COUNTER – OFFSET 80h............................. 92 14.1.46 CAPABILITY ID REGISTER – OFFSET B0h ............................................................. 92 14.1.47 NEXT POINTER REGISTER – OFFSET B0h ............................................................. 92 14.1.48 SLOT NUMBER REGISTER – OFFSET B0h .............................................................. 92 14.1.49 CHASSIS NUMBER REGISTER – OFFSET B0h ....................................................... 93 14.1.50 CAPABILITY ID REGISTER – OFFSET DCh............................................................. 93 14.1.51 NEXT ITEM POINTER REGISTER – OFFSET DCh ................................................. 93 14.1.52 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh ................. 93 14.1.53 POWER MANAGEMENT DATA REGISTER – OFFSET E0h................................... 94 14.1.54 CAPABILITY ID REGISTER – OFFSET E4h ............................................................. 94 14.1.55 NEXT POINTER REGISTER – OFFSET E4h ............................................................. 94 15 BRIDGE BEHAVIOR.................................................................................................................... 95 15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES .............................................................. 95 15.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER).................................... 95 15.2.1 MASTER ABORT................................................................................................................ 95 15.2.2 PARITY AND ERROR REPORTING ................................................................................ 95 15.2.3 REPORTING PARITY ERRORS ....................................................................................... 96 15.2.4 SECONDARY IDSEL MAPPING ...................................................................................... 96 16 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER................................................................ 96 16.1 BOUNDARY SCAN ARCHITECTURE..................................................................................... 96 16.1.1 TAP PINS ............................................................................................................................ 97 16.1.2 INSTRUCTION REGISTER .............................................................................................. 97 16.2 BOUNDARY SCAN INSTRUCTION SET ................................................................................ 98 16.3 TAP TEST DATA REGISTERS.................................................................................................. 99 16.4 BYPASS REGISTER ................................................................................................................... 99 16.5 BOUNDARY-SCAN REGISTER................................................................................................ 99 16.6 TAP CONTROLLER ................................................................................................................... 99 17 ELECTRICAL AND TIMING SPECIFICATIONS ................................................................. 102 17.1 MAXIMUM RATINGS ............................................................................................................. 102 17.2 DC SPECIFICATIONS .............................................................................................................. 103 17.3 AC SPECIFICATIONS .............................................................................................................. 104 17.4 66MHZ TIMING........................................................................................................................ 104 17.5 33MHZ TIMING........................................................................................................................ 105 17.6 POWER CONSUMPTION ........................................................................................................ 105 18 PACKAGE INFORMATION...................................................................................................... 106 18.1 208-PIN FQFP PACKAGE DIAGRAM .................................................................................... 106 18.2 256-BALL PBGA PACKAGE DIAGRAM ............................................................................... 107 18.3 PART NUMBER ORDERING INFORMATION...................................................................... 107 06-0044 |
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