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DS2431 Datasheet(PDF) 3 Page - Maxim Integrated Products

Part # DS2431
Description  1024-Bit 1-Wire EEPROM
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS2431 Datasheet(HTML) 3 Page - Maxim Integrated Products

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1024-Bit, 1-Wire EEPROM
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: 1-Wire WRITE
Standard speed
60
120
Overdrive speed, VPUP > 4.5V
5
15.5
Write-Zero Low Time
(Notes 2, 16, 17)
tW0L
Overdrive speed
6
15.5
μs
Standard speed
1
15
Write-One Low Time
(Notes 2, 17)
tW1L
Overdrive speed
1
2
μs
IO PIN: 1-Wire READ
Standard speed
5
15 -
Read Low Time
(Notes 2, 18)
tRL
Overdrive speed
1
2 -
μs
Standard speed
tRL +
15
Read Sample Time
(Notes 2, 18)
tMSR
Overdrive speed
tRL +
2
μs
EEPROM
Programming Current
IPROG
(Notes 5, 19)
0.8
mA
Programming Time
tPROG
(Notes 20, 21)
10
ms
At +25°C
200k
Write/Erase Cycles (Endurance)
(Notes 22, 23)
NCY
At +85°C (worst case)
50k
Data Retention
(Notes 24, 25, 26)
tDR
At +85°C (worst case)
40
Years
Note 1:
Specifications at TA = -40°C are guaranteed by design only and not production tested.
Note 2:
System requirement.
Note 3:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more
heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 4:
Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2k
Ω resistor is used to pull
up the data line, 2.5µs after VPUP has been applied, the parasite capacitance does not affect normal communications.
Note 5:
Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 6:
VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of
VTL, VTH, and VHY.
Note 7:
Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8:
The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level.
Note 9:
Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0.
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.
Note 14: Defines maximum possible bit rate. Equal to tW0LMIN + tRECMIN.
Note 15: Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS2431 present.
Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN.
Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards. See the
Comparison Table.
Note 17:
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF -
ε and tW0LMAX + tF - ε, respectively.
Note 18:
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.


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