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74ALVC573 Datasheet(PDF) 4 Page - NXP Semiconductors |
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74ALVC573 Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 17 page 74ALVC573_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 26 October 2007 4 of 17 NXP Semiconductors 74ALVC573 Octal D-type transparent latch; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 6. Pin configuration SO20 and TSSOP20 Fig 7. Pin configuration DHVQFN20 573 OE VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 001aad099 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aad100 573 Transparent top view Q7 D6 D7 Q6 D5 Q5 D4 Q4 D3 Q3 D2 Q2 D1 Q1 D0 Q0 9 12 8 13 7 14 6 15 GND(1) 5 16 4 17 3 18 2 19 terminal 1 index area Table 2. Pin description Symbol Pin Description D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input LE 11 latch enable input (active HIGH) OE 1 output enable input (active LOW) Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state latch output VCC 20 supply voltage GND 10 ground (0 V) |
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