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SM89516AL25 Datasheet(PDF) 9 Page - SyncMOS Technologies,Inc |
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SM89516AL25 Datasheet(HTML) 9 Page - SyncMOS Technologies,Inc |
9 / 22 page SyncMOS Technologies International, Inc. SM89516A 8-Bits Micro-controller With 64KB flash & 1KB RAM embedded Specifications subject to change without notice contact your sales representatives for the most recent information. Ver 2.1 SM89516A 08/2006 9 3.Watch Dog Timer The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. User should check WDR bit of SCONF register whenever un-predicted reset happened The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway. There is a 250KHz RC oscillator embedded in chip. Set WDTE = “1” will enable the RC oscillator and the frequency is independent to the system frequency. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM8958A been reset, either hardware reset or WDT reset. To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning. 3.1 Watch Dog Timer Registers: Watch Dog Timer Registers - WDT Control Register (WDTC, $9F) bit-7 bit-0 WDTE R Clear Unused Unused PS2 PS1 PS0 Read / Write: R/W - R/W - - R/W R/W R/W Reset value: 0 * 0 * * 0 0 0 WDTE : Watch Dog Timer enable bit CLEAR : Watch Dog Timer reset bit PS[2:0] : Overflow period select bits PS [2:0] Overflow Period (ms) 000 2.048 001 4.096 010 8.192 011 16.384 100 32.768 101 65.536 110 131.072 111 262.144 |
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