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74ACT11112 Datasheet(PDF) 3 Page - Texas Instruments

Part # 74ACT11112
Description  DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

74ACT11112 Datasheet(HTML) 3 Page - Texas Instruments

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74ACT11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2–3
recommended operating conditions
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
–24
mA
IOL
Low-level output current
24
mA
Dt/Dv
Input transition rise or fall rate
0
10
ns/ V
TA
Operating free-air temperature
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH =50 mA
4.5 V
4.4
4.4
IOH = – 50 mA
5.5 V
5.4
5.4
VOH
IOH =24 mA
4.5 V
3.94
3.8
V
IOH = – 24 mA
5.5 V
4.94
4.8
IOH = – 75 mA†
5.5 V
3.85
IOL =50 mA
4.5 V
0.1
0.1
IOL = 50 mA
5.5 V
0.1
0.1
VOL
IOL =24mA
4.5 V
0.36
0.44
V
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA†
5.5 V
1.65
II
VI = VCC or GND
5.5 V
± 0.1
±1
mA
ICC
VI = VCC or GND,
IO = 0
5.5 V
4
40
mA
DICC‡
VI = VCC or GND
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5 V
3.5
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This parameter is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
125
125
MHz
t
Pulse duration
PRE or CLR low
4
4
ns
tw
Pulse duration
CLK high or low
4
4
ns
t
Setup time before CLK
Data high or low
3.5
4.5
ns
tsu
Setup time before CLK
PRE or CLR inactive
2
2
ns
th
Hold time after CLK
1.5
1.5
ns


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