TDA9935HW datasheet(8/18 Pages) NXP

Part #	TDA9935HW

Description	Dual 14-bit, up to 160 Msample/s, 2 쨈 interpolating Digital-to-Analog Converter (DAC)

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Manufacturer	NXP [NXP Semiconductors]

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TDA9935_4

Product data sheet

Rev. 04 — 17 September 2007

8 of 18

NXP Semiconductors

TDA9935

Dual 14-bit, up to 160 Msample/s, 2

× interpolating DAC

10. Characteristics

Table 5.

Characteristics

VCCD =VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = −40 °C to +85 °C; typical values measured at

VCCD =VCCA = 3.3 V, IO(FS) = 20 mA and Tamb =25 °C; dynamic parameters measured using output schematic given in

Figure 10; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

VCCD

digital supply voltage

3.0

3.3

3.6

V

VCCA

analog supply voltage

3.0

3.3

3.6

V

ICCD

digital supply current

-

55

65

mA

ICCA

analog supply current

-

73

85

mA

Ptot

total power dissipation

fCLK = 80 Msample/s;

fIOUT =fQOUT = 5 MHz

-

422

540

mW

Clock inputs (CLK and CLKN)

VI(CM)

common mode input

voltage

-

1.65

-

V

∆VCLK

differential input voltage

swing

-

1.0

-

V

Analog outputs (IOUT, IOUTN, QOUT and QOUTN)

IO(FS)

full-scale output current

differential outputs

4

-

20

mA

Ro

output resistance

[1] -

150

-

k

Ω

Co

output capacitance

[1] -3

-pF

Digital inputs (I0 to I13, Q0 to Q13 and GAPD)

VIL

LOW-level input voltage

DGND

-

0.3VCCD V

VIH

HIGH-level input voltage

0.7VCCD -VCCD

V

IIL

LOW-level input current

VIL = 0.3VCCD

-5

-

µA

IIH

HIGH-level input current

VIH = 0.7VCCD

-5

-

µA

Reference voltage output (GAPOUT)

VGAPOUT

output voltage

-

1.31

-

V

IGAPOUT

output current

external voltage

-

1

-

µA

∆VGAPOUT output voltage drift

-

±133

-

ppm/

°C

Clock timing inputs (CLK and CLKN)

fCLK(max)

maximum clock rate

80

-

Msample/s

tW(CLKH)

clock HIGH pulse width

5

-

ns

tW(CLKL)

clock LOW pulse width

5

-

ns

Input timing (I0 to I13 and Q0 to Q13); see Figure 5

th(i)

input hold time

1.1

-

3.4

ns

tsu(i)

input setup time

−1.5

-

+0.7

ns

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