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SM8051 Datasheet(PDF) 5 Page - SyncMOS Technologies,Inc |
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SM8051 Datasheet(HTML) 5 Page - SyncMOS Technologies,Inc |
5 / 16 page May 2001 Specifications subject to change without notice,contact your sales representatives for the most recent information. 5/16 Ver 1.1 SM8051/8052 07/2005 SyncMOS Technologies Inc. SM8051/8052 B ACC PSW T2CON RC2L RC2H TL2 TH2 IP SCONF P3 IE P2 SCON SBUF WDTC P1 TCON TMOD TL0 TL1 TH0 TH1 P0 SP DPL DPH (Reserved) PCON SFR Memory MAP $F8 $F0 $E8 $E0 $D8 $D0 $C8 $C0 $B8 $B0 $A8 $A0 $98 $90 $88 $80 $FF $F7 $EF $E7 $DF $D7 $CF $C7 $BF $B7 $AF $A7 $9F $97 $8F $87 Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM8051/8052 Extension Function Description Watch Dog Timer The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. The WDT function can help user software recover form abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. The SM8051/8052 WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM8051/8052 been reset, either hardware reset or WDT reset. To reset the WDT is done by setting 1 to the bit 5 (CLEAR) of WDTC. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning. |
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