Electronic Components Datasheet Search |
|
PEX8612-AA50BCG Datasheet(PDF) 1 Page - PLX Technology |
|
PEX8612-AA50BCG Datasheet(HTML) 1 Page - PLX Technology |
1 / 4 page Preliminary - PLX Confidential PCIe Gen2, 5.0GT/s 12-lane, 3-port Switch Features PEX 8612 General Features o 12-lane, 3-port PCIe Gen2 switch - Integrated 5.0 GT/s SerDes o 19 x 19mm 2, 324-pin FCBGA package o Typical Power: < 2.5 Watts PEX 8612 Key Features o Standards Compliant - PCI Express Base Specification, r2.0 (backwards compatible w/ PCIe r1.0a/1.1) - PCI Power Management Spec, r1.2 - Microsoft Vista Compliant - Supports Access Control Services - Dynamic link-width control - Dynamic SerDes speed control o High Performance - Non-blocking switch fabric - Full line rate on all ports - Packet Cut-Thru with 150ns max packet latency (x4 to x4) - 2KB Max Payload Size - Read Pacing (bandwidth throttling) - Dual-Cast o Flexible Configuration - Ports configurable as x1, x2, x4 - Registers configurable with strapping pins, EEPROM, I 2C, or host software - Lane and polarity reversal - Compatible with PCIe 1.0a PM o Dual-Host & Fail-Over Support - Configurable Non-Transparent port - Moveable upstream port - Crosslink port capability o Quality of Service (QoS) - Eight traffic classes per port - Weighted round-robin source port arbitration o Reliability, Availability, Serviceability - 2 Hot Plug Ports with native HP Signals - All ports hot plug capable thru I 2C (Hot Plug Controller on every port) - ECRC and Poison bit support - Data Path parity - Memory (RAM) Error Correction - INTA# and FATAL_ERR# signals - Advanced Error Reporting - Port Status bits and GPIO available - Per port error diagnostics - Performance Monitoring • Per port payload & header counters - JTAG AC/DC boundary scan The ExpressLane TM PEX 8612 device offers PCI Express switching capability enabling users to add scalable high bandwidth, non-blocking interconnection to a wide variety of applications including workstations, storage systems, communications platforms, embedded systems, and intelligent I/O modules. The PEX 8612 is well suited for fan-out, aggregation, and peer-to-peer applications. High Performance & Low Packet Latency The PEX 8612 architecture supports packet cut-thru with a maximum latency of 150ns (x4 to x4). This, combined with large packet memory and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a max payload size of 2048 bytes, enabling the user to achieve even higher throughput. Data Integrity The PEX 8612 provides end-to-end CRC (ECRC) protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory (RAM) error correction as packets pass through the switch. Flexible Register & Port Configuration The PEX 8612’s 3 ports can be configured to lane widths of x1, x2, or x4. Flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction. Any port can be designated as the upstream port, which can be changed dynamically. The PEX 8612 also provides several ways to configure its registers. The device can be configured through strapping pins, I 2C interface, host software, or an optional serial EEPROM. This allows for easy debug during the development phase, performance monitoring during the operation phase, and driver or software upgrade. Figure 1 shows some of the PEX 8612’s common port configurations. PEX 8612 Version 0.8 2007 Figure 1. Common Port Configurations PEX 8612 PEX 8612 x4 x4 NT PEX 8612 PEX 8612 PEX 8612 PEX 8612 x4 x4 NT PEX 8612 PEX 8612 x4 x4 x4 PEX 8612 PEX 8612 x4 x2 x2 PEX 8612 PEX 8612 PEX 8612 PEX 8612 x4 x4 x4 PEX 8612 PEX 8612 PEX 8612 PEX 8612 x4 x2 x2 |
Similar Part No. - PEX8612-AA50BCG |
|
Similar Description - PEX8612-AA50BCG |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |