PLX Confidential

PCI Express™ Switch for Graphics Fan-Out

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Features

PEX 8547 General Features

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48-lane PCI Express switch

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Three configurable ports

(x1, x2, x4, x8, x16)

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Integrated SerDes

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37.5mm x 37.5mm, 736 pin PBGA package

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Typical Power: 4.9 Watts

PEX 8547 Key Features

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Standards Compliant

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PCI Express Base Specification, r1.1

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High Performance

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Packet Cut Through

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Packet Latency of 110ns (x16 to x16)

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Non-blocking Switch Fabric

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Full Line rate

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Flexible Configuration

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Three configurable ports

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Flexible lane width/port x1, x2, x4, x8, 16

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Configurable with strapping pins,

EEPROM, Host software or I

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Lane and polarity reversal

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PCI Express Power Management

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Link power management states: L0, L0s,

L1, L2/L3 Ready, and L3

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Device states: D0 and D3hot

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INTA and FATAL ERROR signal support

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Port Status bits and GPO available

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Quality of Service (QoS)

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Eight Traffic Classes per port

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Round Robin and Weighted RR port

arbitration

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Reliability, Availability, Serviceability

(RAS)

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Error reporting in addition to Advanced

Error Reporting support of PCI Express

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Per port performance monitoring

• Average packet size, number of

packets, CRC errors

• JTAG boundary scan

Multi-Purpose, Feature Rich PCI Express* ExpressLane™ Switch

The ExpressLane PEX 8547 device offers PCI Express switching

capability conforming to the latest revision of the PCI Express Base

specification (r1.1). This device enables users to add scalable high

bandwidth, non-blocking interconnects to high-end graphics

applications. The PEX 8547 is designed to support graphics or data

aggregation while supporting peer-to-peer traffic for high resolution

graphics applications.

High Performance

The ExpressLane PEX 8547 architecture supports packet cut-through

with a latency of 110ns (x16 to x16). This, combined with large

packet memory (256 to 1024 byte maximum payload size) and non-

blocking internal switch architecture, provide full line rate on its ports

for performance hungry applications such as storage servers or storage

switch fabrics.

Low Packet Latency

The PEX 8547 supports packet cut-through with a latency of 110ns

between symmetric (x16) ingress and egress ports. The low latency

enables many applications to achieve high throughput and

performance. In addition to low latency, the device supports a packet

payload size of up to 1024 bytes, enabling the user to achieve even

higher throughput.

Low Power with Granular SerDes Control

The ExpressLane PEX 8547 provides low power capability that is

fully compliant with the PCI Express power management

specification.

Interoperability

The ExpressLane PEX 8547 is designed to be fully compliant with the

PCI-SIG specification. Additionally, it supports auto-negotiation, lane

reversal, and polarity reversal.

Configuration Flexibility

The ExpressLane PEX 8547 provides several ways to configure its

operations. The device can be configured through strapping pins, I

interface, CPU configuration cycles, or an optional serial EEPROM.

This allows for easy debug during the development phase,

performance monitoring during the operation phase, and driver or

software upgrade.

PEX 8547

Version 1.4 2007