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S29PL129N65GAW000 Datasheet(PDF) 10 Page - SPANSION |
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S29PL129N65GAW000 Datasheet(HTML) 10 Page - SPANSION |
10 / 74 page 10 S29PL-N MirrorBit ™ Flash Family S29PL-N_00_A5 June 6, 2007 Data Sheet (Pre limin ar y) 2. Input/Output Descriptions and Logic Symbols Table 2.1 identifies the input and output package connections provided on the device. Figure 2.1 Logic Symbols – PL256N, PL129N, and PL127N Table 2.1 Input/Output Descriptions Symbol Type Description Amax – A0 Input Address bus DQ15 – DQ0 I/O 16-bit data inputs/outputs/float CE# Input Chip Enable input OE# Input Output Enable input WE# Input Write Enable VSS Supply Device ground NC Not connected Pin Not Connected Internally RY/BY# Output Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. VCC Supply Device Power Supply RESET# Input Hardware reset pin CE1#, CE2# Input Chip Enable inputs for S29PL129 device Logic Symbol – PL256N and PL127N Logic Symbol – PL129N Note 1. Amax = 23 for the PL256N and 22 for the PL127N. max+ 1 16 Amax–A0 WP#/ACC RESET# CE# OE# WE# RY/BY# DQ15 – DQ0 VCC 22 16 DQ15 – DQ0 A21 – A0 WP#/ACC RESET# CE1# OE# WE# RY/BY# CE2# VCC |
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