EDE1108ABSE-5C-E datasheet(9/82 Pages) ELPIDA

Part #	EDE1108ABSE-5C-E

Description	1G bits DDR2 SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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EDE1104ABSE, EDE1108ABSE, EDE1116ABSE

Data Sheet E0852E50 (Ver. 5.0)

9

max.

Parameter

Symbol

Grade

× 4

× 8

× 16

Unit

Test condition

Auto-refresh current

IDD5

-8E

-6C

-6E

-5C

-4A

350

335

320

310

350

335

320

310

⎯

335

320

310

mA

tCK = tCK (IDD);

Refresh command at every tRFC (IDD) interval;

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Self-refresh current

IDD6*

7

-8E

-6C

-6E

-5C

-4A

10

⎯

10

mA

Self-Refresh Mode;

CK and /CK at 0V;

CKE

≤ 0.2V;

Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING

Operating current

(Bank interleaving)

IDD7

-8E

-6C

-6E

-5C

-4A

330

305

300

280

340

315

310

300

⎯

360

350

340

mA

all bank interleaving reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = tRCD (IDD)

−1

× tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD),

tFAW = tFAW (IDD), tRCD = 1

× tCK (IDD);

CKE is H, CS is H between valid commands;

Address bus inputs are STABLE during DESELECTs;

Data pattern is same as IDD4W;

Notes: 1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate is specified by AC Input Test Condition.

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all

combinations of EMRS bits 10 and 11.

5. Definitions for IDD

L is defined as VIN

≤ VIL (AC) (max.)

H is defined as VIN

≥ VIH (AC) (min.)

STABLE is defined as inputs stable at an H or L level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between H and L every other clock cycle (once per two clocks) for address and control

signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals

not including masks or strobes.

6. Refer to AC Timing for IDD Test Conditions.

7. When TC

≥ +85°C, IDD6 must be derated by 80%.

IDD6 will increase by this amount (IDD6 will be 18mA), if TC

≥ +85°C and double refresh option is still

enabled.

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EDE1108ABSE-5C-E Datasheet(PDF) 9 Page - Elpida Memory

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