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EDE1104ABSE-6E-E Datasheet(PDF) 1 Page - Elpida Memory |
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EDE1104ABSE-6E-E Datasheet(HTML) 1 Page - Elpida Memory |
1 / 82 page Document No. E0852E50 (Ver. 5.0) Date Published February 2007 (K) Japan Printed in Japan URL: http://www.elpida.com ©Elpida Memory, Inc. 2005-2007 DATA SHEET 1G bits DDR2 SDRAM EDE1104ABSE (256M words × 4 bits) EDE1108ABSE (128M words × 8 bits) EDE1116ABSE (64M words × 16 bits) Specifications • Density: 1G bits • Organization ⎯ 32M words × 4 bits × 8 banks (EDE1104ABSE) ⎯ 16M words × 8 bits × 8 banks (EDE1108ABSE) ⎯ 8M words × 16 bits × 8 banks (EDE1116ABSE) • Package ⎯ 68-ball FBGA (EDE1104/1108ABSE) ⎯ 92-ball FBGA (EDE1116ABSE) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Data rate ⎯ 800Mbps/667Mbps/533Mbps/400Mbps (max.) • 1KB page size (EDE1104/1108ABSE) ⎯ Row address: A0 to A13 ⎯ Column address: A0 to A9, A11 (EDE1104ABSE) A0 to A9 (EDE1108ABSE) • 2KB page size (EDE1116ABSE) ⎯ Row address: A0 to A12 ⎯ Column address: A0 to A9 • Eight internal banks for concurrent operation • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • Burst type (BT): ⎯ Sequential (4, 8) ⎯ Interleave (4, 8) • /CAS Latency (CL): 3, 4, 5 • Precharge: auto precharge option for each burst access • Driver strength: normal/weak • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period 7.8 μs at 0°C ≤ TC ≤ +85°C 3.9 μs at +85°C < TC ≤ +95°C • Operating case temperature range ⎯ TC = 0°C to +95°C Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; center- aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-Die- Termination for better signal quality • Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization • /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation |
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