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ADS8513IBDWR Datasheet(PDF) 7 Page - Texas Instruments |
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ADS8513IBDWR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 24 page www.ti.com STARTING A CONVERSION ADS8513 SLAS486 – JUNE 2007 BASIC OPERATION (continued) If a conversion is not currently in progress, a falling edge on the CONV input places the sample and hold into the hold mode and begins a conversion, as shown in Figure 3 and with the timing given in Table 2. During the conversion, the CONV input is ignored. Starting a conversion does not depend on the state of CS. A conversion can be started once every 25 μs (40-kHz maximum conversion rate). There is no minimum conversion rate. Even though the CONV input is ignored while a conversion is in progress, this input should be held static during the conversion period. Transitions on this digital input can easily couple into sensitive analog portions of the converter, adversely affecting the conversion results (see the Sensitivity to External Digital Signals section of this data sheet for more information). Ideally, the CONV input should go LOW and remain LOW throughout the conversion. It should return HIGH sometime after BUSY goes HIGH. In addition, it should be HIGH prior to the start of the next conversion for a minimum time period given by t5. This will ensure that the digital transition on the CONV input will not affect the signal that is acquired for the next conversion. An acceptable alternative is to return the CONV input HIGH as soon after the start of the conversion as possible. For example, a negative going pulse 100ns wide would make a good CONV input signal. It is strongly recommended that from time t2 after the start of a conversion until BUSY rises, the CONV input should be held static (either HIGH or LOW). During this time, the converter is more sensitive to external noise. Table 2. Conversion and Data Timing, TA = –40°C to 85°C SYMBOL DESCRIPTION MIN TYP MAX UNITS t1 Conversion Plus Acquisition Time 25 μs t2 CONV LOW to All Digital Inputs Stable 19 μs t3 CONV LOW to Initiate a Conversion 0.04 12 μs t4 BUSY Rising to Any Digital Input Active 5 ns t5 CONV HIGH Prior to Start of Conversion (CONV high time) 15 ns t6 BUSY LOW 18 20 μs t7 CONV LOW to BUSY LOW 12 20 ns t8 Aperture Delay (CONV falling edge to actual conversion start) 5 ns t9 Conversion Time 18 20 μs t10 Conversion Complete to BUSY Rising 90 ns t11 Acquisition Time 5 μs t12 CONV LOW to Rising Edge of First Internal DATACLK 0.27 μs t13 Internal DATACLK HIGH 300 410 425 ns t14 Internal DATACLK LOW 300 410 425 ns t15 Internal DATACLK Period 0.6 0.82 0.85 μs t16 DATA Valid to Internal DATACLK Rising 15 35 ns t17 Internal DATACLK Falling to DATA Not Valid 22 37 ns t18 Falling Edge of Last DATACLK to BUSY Rising 1 μs t19 External DATACLK Rising to DATA Not Valid 4 14 ns t20 External DATACLK Rising to DATA Valid 2 12 20 ns t21 External DATACLK HIGH 15 ns t22 External DATACLK LOW 15 ns t23 External DATACLK Period 35 ns t24 CONV LOW to External DATACLK Active 15 ns t25 External DATACLK LOW or CS HIGH to BUSY Rising 1 μs t26 CS LOW to Digital Outputs Enabled 15 ns t27 CS HIGH to Digital Outputs Disabled 15 ns Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS8513 |
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