DEVICES INCORPORATED

LF3321

Horizontal Digital Image Filter

Improved Performance

LOGIC Devices Incorporated

5

Feb 5, 2003 LDS.3321-A

Video Imaging Products

When interleaved data is fed through the device and an even tap filter is desired, the filter should be

configured for an even number of taps and the I/D Register length should match the number of data sets

interleaved together. When interleaved data is fed through the device and an odd tap filter is desired, the

filter should be set to Odd-Tap Interleave Mode. Bit 0 of Configuration Register 1 and Configuration Register

3 configures Filters A and B respectively for Odd-Tap Interleave Mode. When the filter is configured for

Odd-Tap Interleave Mode, data from the next to last I/D Register in the forward data path is fed into the

first I/D Register in the reverse data path.

When the filter is configured for an odd number of taps (interleaved or non-interleaved modes), the filter is

structured such that the center data value is aligned simultaneously at the A and B inputs of the last ALU in

the forward data path. In order to achieve the correct result, the user must divide the coefficient by two.

Data reversal circuitry is placed after the multiplexers which route data from the forward data path to the

reverse data path (see Figure 6). When decimating, the data stream must be reversed in order for data to

be properly aligned at the inputs of the ALUs.

Functional Description

ALU

A

B

ALU

A

B

COEF 7

COEF 6

ALU

A

B

ALU

A

B

COEF 7

COEF 6

Delay Stage N 1

ALU

A

B

ALU

A

B

COEF 6

EVEN-TAP MODE

ODD-TAP MODE

ODD-TAP INTERLEAVE MODE

2

COEF 7

2

Delay Stage N

Figure 5. I/D Register Data Paths

Data Reversal

Figure 6. Data Reversal