SYS88000RKX - 85/10/12

ISSUE 1.5 : April 2001

3

* Input pulse levels: 0V to 3.0V

* Input rise and fall times: 5ns

* Input and Output timing reference levels: 1.5V

* Output load: see diagram

* V

AC Test Conditions

Output Load

Operation Truth Table

645

100pF

I/O Pin

1.76V

Ω

Parameter

Symbol

Test Condition

min

max

Unit

V

V

DR

CS > V

2.0

-

-

V

Data Retention Current

I

CCDR1

(2)

V

-

-

2

mA

Chip Deselect to Data Retention Time t

CDR

See Retention Waveform

0

-

-

ns

Operation Recovery Time

t

R

See Retention Waveform

5.0

-

-

ms

Notes

(1)

Typical figures are measured at 25°C.

(2) This parameter is guaranteed not tested.

(3) Add 840mA to -L CMOS standby currents to obtain industrial temp range parameters.

Low V

CS

OE

WE

DATA PINS

SUPPLY CURRENT

MODE

H

X

X

High Impedance

Standby

L

L

L

Invalid State

~

Invalid

L

L

H

Data Out

Read

L

H

L

Data In

Write

L

H

H

High-Impedance

High-Z

OE must not be tied low permanently.