5

AT88SC0808C

2024HS–SMEM–04/07

Device Operation For

Synchronous

Protocols

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-

nal device. Data on the SDA pin may change only during SCL low time periods (see

Figure 5 on page 6). Data changes during SCL high periods will indicate a start or stop

condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition

which must precede any other command (see Figure 6 on page 6).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.

After a read sequence, the stop command will place the EEPROM in a standby power

mode (see Figure 6 on page 6).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the

EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has

received each word. This happens during the ninth clock cycle.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-

wire part can be reset by following these steps:

1.

Clock up to 9 cycles.

2.

Look for SDA high in each cycle while SCL is high.

3.

Create a start condition.

Figure 3. Bus Timing for 2 wire communications

SCL: Serial Clock, SDA: Serial Data I/O

Figure 4. Write Cycle Timing:

SCL: Serial Clock, SDA: Serial Data I/O

Note:

The write cycle time t

end of the internal clear/write cycle.

t

WR

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA