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MU9C8480B-50TBC Datasheet(PDF) 8 Page - MUSIC Semiconductors |
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MU9C8480B-50TBC Datasheet(HTML) 8 Page - MUSIC Semiconductors |
8 / 32 page LANCAM B Family Operational Characteristics 8 Rev. 5.1 OPERATIONAL CHARACTERISTICS Note: Throughout the following, “aaaH” represents a three-digit hexadecimal number “aaa,” while “bbB” represents a two-digit binary number “bb.” All memory locations are written to or read from in 16-bit segments. Segment 0 corresponds to the lowest order bits (bits 15–0) and Segment 3 corresponds to the highest order bits (bits 63–48). Control Bus Refer to Figure 1 on page 2 for the following discussion. The inputs Chip Enable (/E), Write Enable (/W), Command Enable (/CM), and Enable Daisy Chain (/EC) are the primary control mechanism for the LANCAM. The /EC input of the Control bus enables the /MF Match flag output when LOW and controls the daisy chain operation. Instructions are the secondary control mechanism. Logical combinations of the Control Bus inputs, coupled with the execution of Select Persistent Source (SPS), Select Persistent Destination (SPD), and Temporary Command Override (TCO) instructions allow the I/O operations to and from the DQ15–0 lines to the internal resources, as shown in Table 2. The Comparand register is the default source and destination for Data Read and Write cycles. This default state can be overridden independently by executing a Select Persistent Source or Select Persistent Destination instruction, selecting a different source or destination for data. Subsequent Data Read or Data Write cycles access that source or destination until another SPS or SPD instruction is executed. The currently selected persistent source or destination can be read back through a TCO PS or PD instruction. The sources and destinations available for persistent access are those resources on the 64-bit bus: Comparand register, Mask Register 1, Mask Register 2, and the Memory array. The default destination for Command Write cycles is the Instruction decoder, while the default source for Command Read cycles is the Status register. Temporary Command Override (TCO) instructions provide access to the Control register, the Page Address register, the Segment Control register, the Address register, the Next Free Address register, and Device Select register. TCO instructions are active only for one Command Read or Write cycle after being loaded into the Instruction decoder. The data and control interfaces to the LANCAM are synchronous. During a Write cycle, the Control and Data inputs are registered by the falling edge of /E. When writing to the persistently selected data destination, the Destination Segment counter is clocked by the rising edge of /E. During a Read cycle, the Control inputs are registered by the falling edge of /E, and the Data outputs are enabled while /E is LOW. When reading from the persistently selected data source, the Source Segment counter is clocked by the rising edge of /E. The Register Set The Control, Segment Control, Address, Mask Register 1, and the Persistent Source and Destination registers are duplicated, with one set termed the Foreground set and the other the Background set. The active set is chosen by issuing Select Foreground Registers or Select Background Registers instructions. By default, the Foreground set is active after a reset. Having two alternate sets of registers that determine the device configuration allows for a rapid return to a foreground network filtering task from a background housekeeping task. Writing a value to the Control register or writing data to the last segment of the Comparand or either Mask register causes an automatic comparison to occur between the contents of the Comparand register and the words in the CAM segments of the memory marked valid, masked by MR1 or MR2 if selected in the Control register. Instruction Decoder The Instruction decoder is the write-only decode logic for instructions and is the default destination for Command Write cycles. If an instruction’s Address Field flag (bit 11) is set to a 1, it is a two-cycle instruction that is not executed immediately. For the next cycle only, the data from a Command Write cycle is loaded into the Address register and the instruction then completes at that address. The Address register then increments, decrements, or stays at the same value depending on the setting of Control Register bits CT3 and CT2. If the Address Field flag is not set, the memory access occurs at the address currently contained in the Address register. Control Register (CT) The Control register contains a number of switches that configure the LANCAM, as shown in Control Register Bits on page 23. It is written or read using a TCO CT instruction. If bit 15 of the value written during a TCO CT is a 0, the device is reset (and all other bits are ignored). See Table 3 on page 11 for the Reset states. Bit 15 always reads back as a 0. A write to the Control register causes an automatic compare to occur (except in the case of a reset). Either the Foreground or Background Control register is active, depending on which register set has been selected, and only the active Control register is written to or read from. If the Match Flag is disabled through bit 14 and bit 13, the internal match condition, /MA(int), used to determine a daisy-chained device’s response is forced HIGH as shown in Table 4 so that Case 6 is not possible, effectively |
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