Rev. 2

4

PIN DESCRIPTIONS

Continued

/RESET (Reset, Input, TTL)

/RESET must be driven LOW to place the device in a known

state before operation, which will reset the device to the

conditions shown in Table 5. The /RESET pin should be

driven by TTL levels, not directly by an RC timeout. /E

must be kept HIGH during /RESET.

TEST1, TEST2 (Test, Input, TTL)

These pins enable MUSIC production test modes that are

not usable in an application. They should be connected to

ground, either directly or through a pull-down resistor, or

they may be left unconnected. These pins may not be

implemented on all versions of these products.

VCC, GND (Positive Power Supply, Ground)

These pins are the power supply connections to the

WidePort LANCAM. VCC must meet the voltage supply

requirements in the Operating Conditions section relative

to the GND pins, which are at 0 Volts (system reference

potential), for correct operation of the device. All the

ground and power pins must be connected to their

respective planes with adequate bulk and high frequency

bypassing capacitors in close proximity to the device.

The MU9C2485A/L and MU9C1485A/L are compatible

with the original MU9C1485 connections, and may be

operated at -90 or slower switching characteristics

without the GND connections on pins 1, 2, 20, 21, 22, 41,

42, 60, 61, and 62.

FUNCTIONAL DESCRIPTION

The WidePort LANCAM is a content-addressable

memory (CAM) with 32-bit I/O for network address

filtering, virtual memory, data compression, caching, and

table lookup applications. The memory consists of static

CAM, organized in 64-bit data fields. Each data field can

be partitioned into a CAM and a RAM subfield on 16-bit

boundaries. The contents of the memory can be randomly

accessed or associatively accessed by the use of a

compare. During automatic comparison cycles, data in

the Comparand register is automatically compared with

the “Valid” entries in the memory array. The Device ID can be

read using a TCO PS instruction (see Table 13).

The data inputs and outputs of the WidePort LANCAM

are multiplexed for data and instructions over a 32-bit

I/O bus. Internally, data is handled on a 64-bit basis,

since the Comparand register, the mask registers, and

each memory entry are 64 bits wide. Memory entries are

globally configurable into CAM and RAM segments on

16-bit boundaries, as described in US Patent 5,383,146

assigned to MUSIC Semiconductors. Seven different

CAM/RAM splits are possible, with the CAM width

going from one to four segments, and the remaining RAM

width going from three to zero segments. Finer resolution

on compare width is possible by invoking a mask register

during a compare, which does global masking on a bit

basis. The CAM subfield contains the associative data,

which enters into compares, while the RAM subfield

contains the associated data, which is not compared. In

LAN bridges, the RAM subfield can hold, for example,

port-address and aging information related to the

destination or source address information held in the

CAM subfield of a given location. In a translation

application, the CAM field can hold the dictionary

entries, while the RAM field holds the translations, with

almost instantaneous response.

Table 3: DQ Bus Multiplexing

/W

LOW

HIGH

LOW

HIGH

/CM

LOW

LOW

HIGH

HIGH

Cycle Type

Command write

Command read

TCO 2nd cycle

Data write

Data read

“f” Bit

0

1

0

1

X

X

X

X

DQ31–16

Non-TCO Instruction

Non-TCO Instruction

TCO Instruction (Read register)*

TCO Instruction (Write register)

Status Register bits 31–16

Status Register bits 31–16†

Data to CR, MRX, Mem.

Data from CR, MRX, Mem.

DQ15–0

XXXX

Absolute Address

XXXX

Value to Register

Status Register bits 15–0

Register contents*

Data to CR, MRX, Mem.

Data from CR, MRX, Mem.

Notes:

*

†

A CW of a TCO Instruction with the “f” bit set to 0 sets up a Register read in the following cycle. The

following cycle must be a Command Read cycle, otherwise the register read will be cancelled.

Upper 16 bits will be Status Register bits 31–16, except for a read of the Page Address register, in which

case they will be all zeros.