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MU9C2480A-50DC Datasheet(PDF) 11 Page - MUSIC Semiconductors |
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MU9C2480A-50DC Datasheet(HTML) 11 Page - MUSIC Semiconductors |
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11 / 32 page  Operational Characteristics LANCAM A/L series (not recommended for new designs) Rev. 1 11 Page Address Register (PA) The Page Address register is loaded using a TCO PA instruction followed by a Command Write cycle of a user selected 16-bit value (not FFFFH). The entry in the PA register gives a unique address to the different devices in a daisy chain. In a daisy chain, the PA value of each device is loaded using the SFF instruction to advance to the next device, shown in the Setting Page Address Register Values on page 16. A software reset (using the Control register) does not affect the Page Address register. Device Select Register (DS) The Device Select register selects a specific (target) device. The TCO DS instruction sets the 16-bit DS register to the value of the following Command Write cycle. The DS register can be read. A device is selected when its DS is equal to its PA value. In a daisy chain, setting DS = FFFFH selects all devices. However, in this case, the ability to read information out of the device is restricted as shown in Table 4. A software reset (using the Control register) does not affect the Device Select register. Address Register (AR) The Address register points to the CAM memory location to be operated upon when M@[AR] or M@aaaH is part of the instruction. It can be loaded directly by using a TCO AR instruction or indirectly by using an instruction requiring an absolute address, such as MOV aaaH,CR,V. After being loaded, the Address register value is the next memory access referencing the Address register. A reset sets the Address register to zero. Control Register bits CT3 and CT2 set the Address register to automatically increment or decrement (or not change) during sequences of Command or Data cycles. The Address register changes after executing an instruction that includes M@[AR] or M@aaaH, or after a data access to the end limit segment (as set in the Segment Control register) when the persistent source or destination is M@[AR] or M@aaaH. Either the Foreground or Background Address register is active, depending on which register set is selected, and only the active Address register is written to or read from. Next Free Address Register (NF) The LANCAM automatically stores the address of the first empty memory location in the Next Free Address register, which is then used as a memory address pointer for M@NF operations. The Next Free Address register, shown in Next Free Address Bits on page 24, can be read using a TCO NF instruction. By taking /EC LOW during the TCO NF instruction cycle, only the device with /FI LOW and /FF HIGH outputs the contents of its Next Free Address register, giving the Next Free address in a system of daisy-chained devices. The Next Free address may be read from a specific device in the chain by setting the Device Select register to the value of the desired device’s Page address and leaving /EC HIGH. The Full Flag daisy chain causes only the device whose /FI input is LOW and /FF output HIGH to respond to an instruction using the Next Free address. After a reset, the Next Free Address register is set to zero. Table 3: Device Control State After Reset CAM Status /RESET Condition Validity bits at all memory locations Match and Full Flag outputs IEEE 802.3–802.5 Input Translation CAM/RAM Partitioning Comparison Masking Address register auto-increment or auto-decrement Source and Destination Segment counters count ranges Address register and Next Free Address register Page Address and Device Select registers Control register after reset (including CT15) Persistent Destination for Command writes Persistent Source for Command reads Persistent Source and Destination for Data reads and writes Operating Mode Configuration Register set Skip = 0, Empty = 1 (empty) Enabled Not translated 64 bits CAM, 0 bits RAM Disabled Disabled 00B to 11B; loaded with 00B Contain all 0s Contain all 0s (no change on software reset) Contains 0008H Instruction decoder Status register Comparand register Standard Foreground |
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