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MU9C8K64-35TDC Datasheet(PDF) 5 Page - MUSIC Semiconductors |
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MU9C8K64-35TDC Datasheet(HTML) 5 Page - MUSIC Semiconductors |
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5 / 35 page  Pin Descriptions MU9C RCP Family Rev. 8.04 5 PA3-0 (Page Address, Output) The PA3-0 lines convey Page Address information. When the /OE input is HIGH, the PA3-0 outputs are in their high-impedance state; when /OE is LOW the PA3-0 lines carry the Page Address value held in the Configuration register. The PA3-0 lines are latched when /E is LOW, and are free to change only when /E is HIGH. The Page Address value of the currently active or highest-priority responding device is output at the same time, and under the same conditions, as the AA bus is active. /E (Chip Enable, Input) The /E input is the main chip enable and synchronizing control for the MU9C RCP. When /E is HIGH, the chip is disabled and the DQ31-0 lines are held in their high-impedance state. The falling edge of /E registers the /W, /CS1, /CS2, /AV, /AC bus, DSC, and the /VB and DQ31-0 lines for a Write cycle. /E being LOW causes the results of the previous comparison or memory access to be latched on the PA:AA bus; when /E goes HIGH the latches open allowing the new comparison results or random access memory address to flow to the PA:AA bus. /CS1, /CS2 (Chip Select 1, Chip Select 2, Inputs) The /CS1 and /CS2 inputs enable the MU9C RCP. If either /CS1 or /CS2 are LOW, the device is selected for a Read, Write, or Compare cycle through the DQ31-0 lines, or for an internal data transfer. The /CS1 and /CS2 lines do not have any effect on the PA:AA bus. The state of the /CS1 and /CS2 lines is registered by the falling edge of /E. /W (Write Enable, Input) The /W input determines the direction of data transfer on the DQ31-0 lines during Read, Write, and Data Move cycles. When /W is LOW, data flows into the DQ31-0 lines; when /W is HIGH, data flows out. The /W line also conditions the control state present on the AC bus and DSC lines. The state of the /W line is registered by the falling edge of /E. /OE (Output Enable, Input) The /OE input enables the PA:AA bus. When /OE is HIGH, PA:AA bus are in their high-impedance state. When /OE is LOW, PA:AA bus are active, and convey the results of the last Comparison Cycle Match address or Memory Access address. In a vertically cascaded system, only the PA:AA bus of the highest-priority device will be activated by /OE being LOW; in lower-priority devices, the PA:AA bus remains in high-impedance regardless of the state of /OE. /AV (Address Valid, Input) When Hardware control is selected, the /AV input determines whether the AC bus carries address or control information. When /AV is LOW, the AC bus conveys a memory address; when /AV is HIGH, the AC bus conveys control information. The state of the /AV line is registered by the falling edge of /E. When software control is selected, the /AV line distinguishes between instructions and data on the DQ31-0 lines; when /AV is LOW, data is present on the DQ31-0 lines; when /AV is HIGH, an instruction is present on the DQ11-0 lines. /VB (Validity Bit, Three-state, Common Input/ Output) During accesses over the DQ31-0 lines, the /VB line conveys validity information to and from the MU9C RCP. During a Write cycle (/W=LOW), when /VB is LOW the addressed location is set valid; when /VB is HIGH it is set empty. During a Read cycle (/W=HIGH), the validity of the addressed location is read on the /VB line. During a Write cycle, the state of the /VB line is registered by the falling edge of /E. /MF (Match Flag, Output) The /MF output indicates whether a valid match has occurred during the previous Comparison cycle. If the /MF output is HIGH at the end of a Comparison cycle, then no match occurred; if it is LOW then either a match occurred within the device, or the /MI input is LOW, conditioned by the /MF output from a higher-priority device in the system. The state of the /MF line will not change until after the rising edge of /E during the Comparison cycle. Note that /MF indicates the results of the most recent Comparison cycle; it will not change when the PA:AA bus carry an address other than the Match address. /MI (Match Input, Input) The /MI input receives match information from the next higher-priority MU9C RCP in a vertically cascaded system to provide system-level prioritization. When the /MI input is HIGH, the /MF output will only go LOW if there is a match during a Comparison cycle; when the /MI input is LOW, the /MF output will go LOW. The /MF output from one device is connected to the /MI input of the next lower-priority device. The /MI pin of the highest-priority device must be tied HIGH. |
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