MT88E43BS datasheet(8/29 Pages) ZARLINK

Part #	MT88E43BS

Description	Extended Voltage Calling Number Identification Circuit 2

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Manufacturer	ZARLINK [Zarlink Semiconductor Inc]

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MT88E43B

Data Sheet

8

Zarlink Semiconductor Inc.

Figure 5 - Guard Time Circuits with Unequal Times

Input Configuration

The MT88E43 provides an input arrangement comprised of an operational amplifier and a bias source (VRef); which

is used to bias the opamp inputs at VDD/2. The feedback resistor at the opamp output (GS) can be used to adjust

the gain. In a single-ended configuration, the opamp is connected as shown in Figure 6. For a differential input

configuration, Figure 7 shows the necessary connections.

Figure 6 - Single-Ended Input Configuration

(b) tGP < tGA

tGP = RPC ln [VDD-VD(RP/R2))/(VDD-VTGt-VD(RP/R2))]

tGA = R1C ln (VDD/VTGt)

RP = R1R2/(R1+R2)

(a) tGP > tGA

tGP = R1C ln [VDD/(VDD-VTGt)]

tGA = RPC ln [(VDD-VD(RP/R2))/(VTGt-VD(RP/R2))]

RP = R1R2/(R1+R2)

MT88E43

VDD

St/GT

ESt

R1

R2

C

VDD

St/GT

ESt

R1

R2

C

MT88E43

VD=diode forward voltage

C

RIN

IN+

IN-

GS

VRef

Voltage Gain

(AV) = RF / RIN

RF

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