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ADIS16350 Datasheet(PDF) 5 Page - Analog Devices

Part # ADIS16350
Description  Tri-Axis Inertial Sensor
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADIS16350 Datasheet(HTML) 5 Page - Analog Devices

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ADIS16355
Rev. PrG | Page 5 of 28
TIMING SPECIFICATIONS
TA = 25°C, Vcc = 5.0 V, angular rate = 0°/s, unless otherwise noted.
Table 2.
Parameter
Description
Min1
Typ
Max1
Unit
fSCLK
Fast mode, SMPL_PRD ≤ 0x09 (fS ≥ 164 Hz)
0.01
2
MHz
Normal mode, SMPL_PRD ≥ 0x0A (fS ≤ 149 Hz)
10
300
kHz
tDATARATE
Data rate time, fast mode, SMPL_PRD ≤ 0x09 (fS ≥ 164 Hz)
40
μs
Data rate time, normal mode, SMPL_PRD ≥ 0x0A (fS ≤ 149 Hz)
160
μs
tDATASTALL
Data stall time, fast mode SMPL_PRD ≤ 0x09 (fS ≥ 164 Hz)
9
μs
Data stall time, normal mode SMPL_PRD ≥ 0x0A (fS ≤ 149 Hz)
75
μs
tCS
Chip select to clock edge
48.8
ns
tDAV
Data output valid after SCLK falling edge2
100
ns
tDSU
Data input setup time before SCLK rising edge
24.4
ns
tDHD
Data input hold time after SCLK rising edge
48.8
ns
tDF
Data output fall time
5
12.5
ns
tDR
Data output rise time
5
12.5
ns
tSFS
CS high after SCLK edge3
5
ns
1 Guaranteed by design, not production tested.
2 The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked after the falling edge of SCLK and
are governed by this specification.
3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.
TIMING DIAGRAMS
CS
SCLK
tDATARATE
tDATASTALL
Figure 2. SPI Chip Select Timing
CS
SCLK
DOUT
DIN
1
2
3
4
5
6
15
16
W/R
A5
A4
A3
A2
D2
MSB
DB14
D1
LSB
DB13
DB12
DB10
DB11
DB2
LSB
DB1
tCS
tSFS
tDAV
tDHD
tDSU
Figure 3. SPI Timing, Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1


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