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HF88S05 Datasheet(PDF) 8 Page - King blillion Electronics Co.,Ltd. |
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HF88S05 Datasheet(HTML) 8 Page - King blillion Electronics Co.,Ltd. |
8 / 13 page KING BILLION ELECTRONICS CO., LTD 駿 億 電 子 股 份 有 限 公 司 HF88S05 SRAM Series December 18, 2003 8 V1.00 This specification is subject to change without notice. Please contact sales person for the latest version before use. Checksum and SRAM contents can also be read through Serial Interface, too. The Serial Data Input SDI pin is connected to LSB of internal shift register. With each rising edge of SCLK pin, the SDI input is shifted into the shift register. At the eighth rising edge of SCLK, the content of shift Register is transferred from/to registers or SRAM depending on the status of D_Cn and R_Wn. If R_Wn is at “high” state at the eighth rising edge of SCLK then either the contents of Checksum Register (if D_Cn is “low”) or SRAM been addressed (if D_Cn is “high”) will be latched into the internal shift register. Then the contents of Shift Register can be shifted out with the next eight rising edges of SCLK. So one thing important should be noted here when using the Serial Data Interface to read checksum register or SRAM data is that one dummy read should be performed before the real data can be shifted out from SDO pin. 7.2. Serial Command Write Mode The sequence of setting up addresses for data transfer is similar to the parallel mode. The register pointer will be reset by accesses to SRAM data in the same way as the parallel mode does. So immediately after completion of previous data transfers or when the device is just selected, the command writes will be made to TPL, TPH then TPP registers and then wrap around. If unsure any time during the transfer, a dummy data read can be made to reset the register select. CS0_n CS1 P_Sn D_Cn R_Wn SDI SCLK TP (TPP, TPH, TPL) b7 xxxxxx Series Command Write Mode SDO b1 b0 b7 b6 b6 b5 b4 b3 b2 b5 b7 b6 b4 b3 b2 b1 b0 Update TPH The bit 7 shall be shifted into register first. Update TPL 7.3. Serial Data Write Mode With each rising edge of SCLK signal in the serial data write mode (P_Sn @ logic ‘0’, R_Wn @ logic ‘0’, and D_Cn @ logic ‘1’), the Data on the SDI pin will be shifted into the internal shift register. The content |
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