1

Rev. I

1/26/07

Copyright © 2005 Integrated Silicon Solution, Inc.

All rights reserved.

ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

IS63LV1024

IS63LV1024L

128K x 8 HIGH-SPEED CMOS STATIC RAM

3.3V REVOLUTIONARY PINOUT

FEATURES

• High-speed access times:

8, 10, 12 ns

• High-performance, low-power CMOS process

• Multiple center power and ground pins for

greater noise immunity

options

• Fully static operation: no clock or refresh

required

• TTL compatible inputs and outputs

• Single 3.3V power supply

• Packages available:

– 32-pin 300-mil SOJ

– 32-pin 400-mil SOJ

– 32-pin TSOP (Type II)

– 32-pin STSOP (Type I)

– 36-pin BGA (8mmx10mm)

• Lead-free Available

DESCRIPTION

The

low power, 131,072-word by 8-bit CMOS static RAM in

revolutionary pinout. The IS63LV1024/IS63LV1024L is fab-

ricated using

This highly reliable process coupled with innovative circuit

design techniques, yields higher performance and low

power consumption devices.

When

CE is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be

reduced down to 250 µW (typical) with CMOS input levels.

The IS63LV1024/IS63LV1024L operates from a single 3.3V

power supply and all inputs are TTL-compatible.

FUNCTIONAL BLOCK DIAGRAM

A0-A16

CE

OE

WE

128K X 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VDD

I/O

DATA

CIRCUIT

I/O0-I/O7

JANUARY 2007