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EN25B16T-100VCP Datasheet(PDF) 8 Page - Eon Silicon Solution Inc. |
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EN25B16T-100VCP Datasheet(HTML) 8 Page - Eon Silicon Solution Inc. |
8 / 36 page This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw or modifications due to changes in technical specifications. 8 EN25B16 Rev. C, Issue Date: 2006/12/22 Status Register.The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. BUSY bit. The BUSY bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRP bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1, BP0) become read-only bits. Write Protection Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the EN25B16 provides the following data protection mechanisms: Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events: – Power-up – Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction completion or Page Program (PP) instruction completion or Sector Erase (SE)instruction completion or Bulk Erase (BE) instruction completion or The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction). Table 3a. Protected Area Sizes- Bottom Boot Sector Organization Status Register Content Memory Content BP2 Bit BP1 Bit BP0 Bit Protect Sectors Addresses Density(KB) Portion 1 1 1 All 000000h-1FFFFFh 2048KB All 1 1 0 Sector 0 to 19 000000h-0FFFFFh 1024KB Lower 1/2 1 0 1 Sector 0 to 4 000000h-00FFFFh 64KB Lower 1/32 1 0 0 Sector 0 to 3 000000h-007FFFh 32KB Lower 1/64 0 1 1 Sector 0 to 2 000000h-003FFFh 16KB Lower 1/128 0 1 0 Sector 0 to 1 000000h-001FFFh 8KB Lower 1/256 0 0 1 Sector 0 000000h-000FFFh 4KB Lower 1/512 0 0 0 None None None None |
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